zig-p4: pure-Zig ESP32-P4 toolchain

build.zig generates the linker script and drives Zig's own LLD; tools/image.zig
turns the ELF into a flashable image and tools/{rom,serial}.zig speak the mask
ROM loader over the UART. No CMake, ninja, idf.py, esptool, or external linker.

src/soc.zig is a comptime register model over ESP-IDF's own *_reg.h headers;
src/hal/ adds peripheral sequences; src/io/ implements std.Io for the chip;
src/oracle/ diffs this HAL against ESP-IDF's on the die.

1 files changed, 56 insertions, 0 deletions

diff --git a/src/net/hosted/pin_assert.c b/src/net/hosted/pin_assert.c
new file mode 100644
index 0000000..8704c7b
--- /dev/null
+++ b/src/net/hosted/pin_assert.c
@@ -0,0 +1,56 @@
+/*
+ * The board, asserted at compile time.
+ *
+ * ESP-Hosted derives its SDIO pin map, bus width, clock and the C6 reset pin from Kconfig, and this
+ * project checks in that Kconfig verbatim as src/net/hosted/sdkconfig.h. That makes the wiring a
+ * build input rather than something written in Zig - which is the right choice, because the real
+ * `struct esp_hosted_sdio_config` interleaves `gpio_pin_t {void *port; int pin;}` pairs and
+ * transcribing it into Zig invites a silent wrong-pin bug.
+ *
+ * The cost of that choice is that the wiring is now several files away from the board. This file
+ * pays it back: every value is asserted against what was measured on the die. If a Kconfig symbol
+ * ever drifts, the build fails naming the pin, instead of the C6 quietly never answering - which
+ * is the same symptom as a dead radio, a wrong clock, or a held reset, and takes an afternoon to
+ * tell apart.
+ *
+ * Measurements: Guition JC-ESP32P4-M3-DEV schematic sheet 5 (schematics/5_ESP32-C6.png in the
+ * unofficial board repo), confirmed against the boot log of the ESP-IDF build in
+ * 02-esp32p4-m3-radio that reached esp_hosted transport state "active" on this die.
+ */
+
+#include "port_esp_hosted_host_config.h"
+
+/* SDIO slot and bus. Slot 1 is the only one routed to the C6 on this board. */
+_Static_assert(H_SDMMC_HOST_SLOT == 1, "SDIO slot: board routes the C6 to slot 1");
+_Static_assert(H_SDIO_BUS_WIDTH == 4, "SDIO bus width: all four data lines are wired");
+_Static_assert(H_SDIO_CLOCK_FREQ_KHZ == 40000, "SDIO clock: 40 MHz was measured working");
+
+/* Pin map. D1 doubles as the slave interrupt line, which is why it must be a real data pin and
+ * not left unconfigured. */
+_Static_assert(H_SDIO_PIN_CLK == 18, "SDIO CLK is GPIO18");
+_Static_assert(H_SDIO_PIN_CMD == 19, "SDIO CMD is GPIO19");
+_Static_assert(H_SDIO_PIN_D0 == 14, "SDIO D0 is GPIO14");
+_Static_assert(H_SDIO_PIN_D1 == 15, "SDIO D1 is GPIO15, and doubles as the slave interrupt");
+_Static_assert(H_SDIO_PIN_D2 == 16, "SDIO D2 is GPIO16");
+_Static_assert(H_SDIO_PIN_D3 == 17, "SDIO D3 is GPIO17");
+
+/* The C6 reset. Active low with an external pull-up: it must be RELEASED, never driven high.
+ * Driving it the other way holds the radio in reset forever while looking like a config detail. */
+_Static_assert(H_GPIO_PIN_RESET == 54, "C6 reset is GPIO54");
+
+/* The coprocessor. H_SLAVE_TARGET_ESP32C6 is what
+ * host/port/esp/freertos/include/port_esp_hosted_host_config.h:65-95 derives from
+ * CONFIG_ESP_HOSTED_CP_TARGET_ESP32C6, and it gates wire-format decisions further up. */
+#ifndef H_SLAVE_TARGET_ESP32C6
+#error "Slave target is not ESP32-C6. The coprocessor on this board is an ESP32-C6-MINI."
+#endif
+
+/* H_USE_MEMPOOL must be DEFINED - its value is a real choice (see sdkconfig.h override 3), but
+ * whether the name exists at all is what decides the length of hosted_osi_funcs_t, because the
+ * struct guards four members with #ifdef. abi_assert.c checks the resulting size directly. */
+#ifndef H_USE_MEMPOOL
+#error "H_USE_MEMPOOL is not defined: the force-include of port_esp_hosted_host_config.h is missing."
+#endif
+
+/* A definition, so the translation unit is not empty. */
+const int esp_hosted_pin_assertions_hold = 1;