zig-p4: pure-Zig ESP32-P4 toolchain

build.zig generates the linker script and drives Zig's own LLD; tools/image.zig
turns the ELF into a flashable image and tools/{rom,serial}.zig speak the mask
ROM loader over the UART. No CMake, ninja, idf.py, esptool, or external linker.

src/soc.zig is a comptime register model over ESP-IDF's own *_reg.h headers;
src/hal/ adds peripheral sequences; src/io/ implements std.Io for the chip;
src/oracle/ diffs this HAL against ESP-IDF's on the die.

1 files changed, 51 insertions, 0 deletions

diff --git a/src/oracle/all.zig b/src/oracle/all.zig
new file mode 100644
index 0000000..9537eac
--- /dev/null
+++ b/src/oracle/all.zig
@@ -0,0 +1,51 @@
+//! Every peripheral registered with the differential harness.
+//!
+//! One line per peripheral. The harness walks this list, so adding a peripheral to the oracle is
+//! three new files (`<name>_ref.c`, `<name>_cases.zig`, `src/hal/<name>.zig`) plus one line here.
+
+pub const types = @import("differ_types.zig");
+
+pub const gpio = @import("gpio_cases.zig");
+pub const clkrst = @import("clkrst_cases.zig");
+pub const timg = @import("timg_cases.zig");
+pub const uart = @import("uart_cases.zig");
+pub const intr = @import("intr_cases.zig");
+pub const ledc = @import("ledc_cases.zig");
+pub const i2c = @import("i2c_cases.zig");
+pub const sdmmc = @import("sdmmc_cases.zig");
+
+/// The suites, in the order they run.
+///
+/// GPIO first: the console's own pins live in that block, so a failure there explains failures
+/// everywhere else. `clkrst` last of the always-on set, because its cases deliberately gate
+/// peripherals off and its restore is what puts them back.
+pub const suites = [_]types.Suite{
+    gpio.suite,
+    gpio.iomux_suite,
+    timg.suite,
+    uart.suite,
+    intr.suite,
+    intr.clic_suite,
+    intr.thresh_suite,
+    // LEDC's state is not contiguous, so it comes as four windows rather than one: the block
+    // itself, the gamma RAM aperture (whose restore has to zero the RAM, because a peripheral reset
+    // does not), the GPIO words its pin routing touches, and the one HP_SYS_CLKRST word the P4
+    // moved its clock mux into.
+    ledc.suite,
+    ledc.gamma_suite,
+    ledc.routing_suite,
+    ledc.clock_suite,
+    // I2C likewise needs two: half of setBusTiming lands outside the I2C block, because the
+    // controller-clock divider is in HP_SYS_CLKRST. At 10 kHz that divider is 4, so an
+    // implementation that wrote all ten timing registers perfectly and the divider not at all would
+    // run the bus four times too fast and pass every case in the first suite.
+    i2c.suite,
+    i2c.clock_suite,
+    // SDMMC, likewise in two windows: the controller block, and the host clock generator that the
+    // P4 put in HP_SYS_CLKRST rather than in the peripheral. At 40 MHz the whole division happens
+    // in the second one, so a suite that covered only the first would pass on a bus running four
+    // times too fast.
+    sdmmc.suite,
+    sdmmc.clock_suite,
+    clkrst.suite,
+};