diff options
| -rw-r--r-- | src/pardes/app.zig | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/pardes/app.zig b/src/pardes/app.zig index 34f427d..1302556 100644 --- a/src/pardes/app.zig +++ b/src/pardes/app.zig @@ -218,7 +218,10 @@ export fn zig_main() noreturn { gpa_heap = heapmod.Heap.init(heap); _ = uart.drainInput(); - const rc = pardes_p4_init(&editor_allocator, writeOut, null, 80, 24); + // Ask for more than any grid this board will ever render, so the SHELL's own ceiling is what + // governs - it clamps to `-Dp4-cols`/`-Dp4-rows` and reports the result. Naming 80x24 here made + // the firmware a second opinion about the geometry, which is one opinion too many. + const rc = pardes_p4_init(&editor_allocator, writeOut, null, 255, 255); if (rc != 0) { soc.rom.print("MARK PARDES_INIT_FAIL rc=%u\r\n", .{rc}); @@ -229,6 +232,17 @@ export fn zig_main() noreturn { while (true) {} } + // The HEAP, after the editor has taken what it needs. This is the number that decides how large + // a grid the board can drive, so it is printed on every boot rather than only on failure: a + // geometry that fits with 2 KB to spare and one that fits with 80 KB are not the same answer, + // and the difference is invisible from the host otherwise. + { + const s = gpa_heap.stats(); + soc.rom.print("MARK PARDES_HEAP free=%u largest=%u blocks=%u\r\n", .{ + s.free, s.largest_free, s.free_blocks, + }); + } + // The CPU clock, measured rather than assumed. Every cycle count this firmware reports is // divided by it somewhere, and `src/io/chip.zig` records it as "a measured ~90 MHz" that // nothing here reconfigures - so it is worth printing rather than remembering. The systimer is |