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diff --git a/cpu-docs/manifests/EspSilicon.md b/cpu-docs/manifests/EspSilicon.md new file mode 100644 index 0000000..c3a5544 --- /dev/null +++ b/cpu-docs/manifests/EspSilicon.md @@ -0,0 +1,28 @@ +# EspSilicon — ESP32-P4 chip-level primary documentation from Espressif (silicon rev v1.3 / pre-v3 focus) + +## Obtained + +| file | title | version / date | source URL | bytes | pages | sha256 (first 16) | relevance | +|---|---|---|---|---|---|---|---| +| espressif-silicon/esp32-p4-chip-revision-v1.3_technical-reference-manual_en_pre-release-v0.4.pdf | ESP32-P4 Chip Revision v1.3 Technical Reference Manual | Pre-release v0.4, 2026-06-11 | https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_technical_reference_manual_en.pdf | 20786220 | 2975 | ae1fa2a411776760 | **Rev-matched pre-v3 TRM (EOL-watermarked).** ch.1 High-Performance CPU p.60 (§1.4 Address Map p.62, §1.5 CSRs p.63 w/ register summary+description, §1.6 RISC-V standard extensions M/C/F/Zc/A p.94-99, §1.9 Interrupt Controller p.111 → §1.9.2 CLIC p.111 / §1.9.2.2 CLIC CSRs / §1.9.2.3 Interrupt Mapping / §1.9.2.5 Interrupt Level and Priority Encoding / §1.9.2.6-7 CLIC memory-mapped regs p.113-115, §1.9.3 CLINT p.118); ch.2 RISC-V Trace Encoder p.159; ch.3 Low-Power CPU p.189; ch.7 System and Memory p.450 (§7.3.1 Address Mapping p.451, §7.3.2 Internal Memory p.454, §7.3.3.1 External Memory Address Mapping p.456 = flash/PSRAM windows 0x4000_0000-0x43FF_FFFF & 0x4800_0000-0x4BFF_FFFF cacheable + 0x8000_0000/0x8800_0000 direct, mapped via MMU, §7.3.3.2 Cache p.457, §7.3.3.3 Cache Operations p.458, §7.3.4 DMA Address Space p.459, §7.3.5 Modules/Peripherals Address Mapping p.460); ch.8 eFuse Controller p.464; ch.10 Reset and Clock p.612; ch.11 Chip Boot Control p.750 (boot-mode control; no separate boot-ROM chapter); ch.12 Interrupt Matrix p.755 (per-core HP CPU0/CPU1 register sets §12.5-12.6); ch.14 Low-Power Management p.952; ch.15 System Timer p.1033; ch.16 Timer Group (TIMG) p.1058; ch.17 Watchdog Timers (WDT) p.1083; ch.18 RTC Timer p.1098; ch.19 Permission Control (PMS) p.1112; ch.20 System Registers (SYSREG) p.1209; ch.21 Debug Assistant p.1301; ch.22 LP Mailbox p.1361 | +| espressif-silicon/esp32-p4-chip-revision-v1.3_datasheet_en_v1.2.pdf | ESP32-P4 Chip Revision v1.3 Datasheet | v1.2, 2026-06-16 | https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v1.3_datasheet_en.pdf | 1603774 | 94 | b2b0ae6fb8e92d23 | Rev-v1.3 spec baseline: HP = 32-bit RISC-V dual-core **RV32IMAFC** (states "supports standard RV32IMAFCZc extensions") up to **360 MHz default** (400 MHz only on request), LP core **RV32IMAC**; on-chip memory 128 KB HP ROM + 16 KB LP ROM + 768 KB HP L2MEM + 8 KB SPM @360 MHz; in-package 16 or 32 MB PSRAM (Table 5-9 PSRAM Specifications); §3 ROM message printing control (Tables 3-5 UART0 / 3-6 USB Serial-JTAG) for boot-log routing; §1 series comparison + revision history (whole doc is the v1.3/EOL line: ESP32-P4NRW16/32 → EOL) | +| espressif-silicon/esp32-p4_soc-errata_en_v1.3.pdf | ESP32-P4 Series SoC Errata | v1.3 (index release 2026-07-10; PDF build 2026-08-23) | https://docs.espressif.com/projects/esp-chip-errata/en/latest/esp32p4/esp-chip-errata-en-master-esp32p4.pdf | 144853 | 19 | 5fd0fec5b306873a | 13 errata. §1.1 vM.X revision scheme; §1.2 runtime chip-rev detection via **EFUSE_RD_MAC_SPI_SYS_2_REG[23] + [5:0]** (Table 1.1 gives the exact bit pattern for v1.3 vs v0.0/v1.0/v3.0/v3.1/v3.2); §1.4 ESP-IDF release compatibility; §2 Errata Summary p.3; §3.3-3.5 MSPI-749 load-access-fault on power-on/deep-sleep wake, MSPI-750 PSRAM unaligned DMA stale data, MSPI-751 address-overlap timing; §3.6/3.7/3.8 ROM-764 secure-boot bad buffer addr, ROM-770 secure-download flash power-on failure, ROM-816 hang on double flash power-on — all boot-ROM issues live on v1.3 silicon; §3.10 DMA-767, §3.11 APM-560 | +| espressif-silicon/esp32-p4-chip-revision-v3.x_user-guide_en_v1.0.pdf | ESP32-P4 Chip Revision v3.x User Guide | v1.0, 2026-03-11 | https://www.espressif.com/sites/default/files/documentation/esp32-p4-chip-revision-v3.x_user_guide_en.pdf | 476336 | 13 | 9329de55ef88f310 | Chip-revision/compatibility doc; §1 "Design Changes in Chip Revision v3.x" is the definitive list of what v1.3 silicon **lacks**: HP CPU max 360 (not 400) MHz, **no Zb extension**, PMP entries fewer than 32, no user-mode interrupt delegation and no Interrupt-Matrix remapping, unfixed EXT_ILL_CSR bit-0 FPU behaviour, slower/less-compliant CLIC CSR access, different HW-loop counter width (v3.x = 24-bit), and cached region mapping starting from the **top** of L2MEM (v3.x moved it to the bottom) — plus §1 lists the v1.3 bugs fixed later (MSPI-749/750/751, ROM-764/770, Analog-765, DMA-767, APM-560); §2 upgrade impact, §4 ordering info | +| espressif-silicon/esp32-p4_technical-reference-manual_en_pre-release-v0.7.pdf | ESP32-P4 Technical Reference Manual | Pre-release v0.7, 2026-08-20 | https://www.espressif.com/sites/default/files/documentation/esp32-p4_technical_reference_manual_en.pdf | 23537234 | 3701 | 622fe9625d19cf00 | Placed by LocalHarvest; I verified it byte-identical (full sha256 match) to current upstream, so not re-downloaded. This is the **v3.x-line** manual, kept because the rev-v1.3 TRM omits the ISA-extension chapter: ch.4 **Processor Instruction Extensions (PIE)** p.210 plus §2.7.1 Hardware Loop p.119 / §2.7.1.2 HWLP Instructions p.126 / §2.7.2 Processor Instruction Extension p.127 exist ONLY here. Other verified in-document chapters (numbering differs from both the v1.3 TRM and this manual's own "Release Status" list, which counts a non-existent eFuse chapter): ch.1 Bus Architecture p.65 (absent from v1.3 TRM), ch.2 HP CPU p.68 (§2.9 Interrupt Controller p.130, §2.9.2 CLIC p.130, §2.9.2.2 CLIC CSRs p.130), ch.5 LP CPU p.633, ch.9 System and Memory p.901 (§9.3.1 Address Mapping p.902, §9.3.2 Internal Memory p.905, §9.3.3.1 External Memory Address Mapping p.909, §9.3.3.2 Cache p.909, §9.3.3.3 Cache Operations p.910, §9.4 eFuse Controller p.916 — eFuse is a *section* here, not a chapter), ch.11 Reset and Clock p.1081, ch.12 Chip Boot Control p.1219, ch.13 Interrupt Matrix p.1224, ch.15 Low-Power Management p.1425, ch.16 System Timer p.1507, ch.17 TIMG p.1532, ch.18 WDT p.1557, ch.19 RTC Timer p.1572, ch.21 SYSREG p.1687, ch.23 AXI Performance Monitor p.1853; register details must be cross-checked against the v1.3 TRM before use on this silicon | +| espressif-silicon/esp32-p4_datasheet_en_pre-release-v0.7.pdf | ESP32-P4 Series Datasheet | Pre-release v0.7, 2026-07-14 | https://www.espressif.com/sites/default/files/documentation/esp32-p4_datasheet_en.pdf | 1576185 | 102 | fb4f3e91cc2ac519 | Placed by LocalHarvest; verified byte-identical to current upstream, not re-downloaded. **v3.x-line only** — its §1.3 "Chip Revision" covers v3.x and explicitly defers rev-identification/older revisions to the SoC Errata and the v3.x User Guide, so it does **not** carry a v1.3 row; quotes 400 MHz RV32IMAFC (+Zc), LP RV32IMAC, 128 KB HP ROM / 768 KB L2MEM (200 MHz) / 8 KB SPM @400 MHz. Use the rev-v1.3 datasheet above for this project's silicon | + +## Not obtained + +| wanted | why not | best known pointer | +|---|---|---| +| Standalone `esp32-p4_errata_en.pdf` on espressif.com | No such file exists. The filtered ESP32-P4 document index lists "ESP32-P4 Series SoC Errata" v1.3 whose only link is the esp-chip-errata docs project HTML page; no `/sites/default/files/documentation/*errata*.pdf` is served for any chip. I fetched the vendor-official PDF build of that same document instead (see Obtained), so the content is archived — only the hypothetical filename is missing. | https://docs.espressif.com/projects/esp-chip-errata/en/latest/esp32p4/index.html | +| ESP32-P4 Chip Revision v1.x User Guide (a v1.3-side counterpart to the v3.x guide) | Not published. The ESP32-P4-filtered document index contains exactly one chip-revision user guide, for v3.x; there is no v1.x/v1.3 equivalent. The v3.x guide covers the delta in the other direction and is archived above. | https://www.espressif.com/en/support/documents/technical-documents (filter Chip = ESP32-P4) | +| ESP32-P4 Consolidated Pin Overview v1.2 (datasheet appendix) | Published only as `.xlsx`; no PDF exists anywhere official. It is a pin-mux/IO table and carries nothing about bootloader, memory map, interrupts, timers, CSRs, or instructions, so it fails the relevance bar for this archive. | https://www.espressif.com/sites/default/files/documentation/ESP32-P4%20Appendix%20Consolidated%20Pin%20Overview.xlsx | +| ESP32-P4 Hardware Design Guidelines v1.9; ESP32-P4 Test Tools and Guidelines; ESP32-P4 Series Product Packaging Information | Deliberately excluded: assignment bars hardware-design/PCB-layout/RF and board-production documents. | https://www.espressif.com/en/support/documents/technical-documents | + +## Belongs elsewhere + +- ESP-IDF Programming Guide for ESP32-P4 (SDK stable v6.0.2 / v5.5.x), esptool.py Programming Guide, ROM bootloader + flash image format, OpenOCD/GDB manuals — should be fetched by `espressif-software/` +- Vendor SIMD/PIE and HWLP instruction encodings — the source document (generic TRM v0.7, ch.4 PIE p.210 and §2.7.1 HWLP p.119) is archived here in `espressif-silicon/`, but the extension-specific extraction/spec work belongs to `espressif-custom-isa/`; note the rev-v1.3 TRM lists ch.3 "Processor Instruction Extensions" as "[to be added later]" and omits it entirely, so PIE must be cited from the v0.7 TRM +- RISC-V unprivileged/privileged ISA, Zc, debug spec, and the fast-interrupt/CLIC draft specification — should be fetched by `riscv-isa/` +- Board/module documents already present at `01-esp32p4-m3/docs/` (JC-ESP32P4-M3 dev-board PDFs, ESP32-C6-MINI-1 module datasheet) — owned by LocalHarvest; out of scope here |