1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
|
# RiscvSpecs — official RISC-V International specifications for the ESP32-P4 HP core (RV32IMAFC_Zicsr_Zifencei, M/U modes, PMP, debug)
## Obtained
| file | title | version / date | source URL | bytes | pages | sha256 (first 16) | relevance |
|---|---|---|---|---|---|---|---|
| riscv-isa/riscv-unprivileged-isa_vol1_ratified_20250508.pdf | The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture | 20250508, Ratified (release tag `20250508`, published 2025-05-12) | https://github.com/riscv/riscv-isa-manual/releases/download/20250508/riscv-unprivileged-20250508.pdf | 4643378 | 727 | cef2e63c08c6f82c | Ch.2 RV32I base, Ch.5 Zifencei, Ch.6 Zicsr, Ch.7.1 Zicntr (cycle/time/instret, CSR 0xC00–0xC1F with high halves at 0xC80–0xC9F, RDCYCLE/RDCYCLEH), Ch.12 M, Ch.13 A, Ch.20 F single-precision, Ch.27 C compressed, Ch.28 Zc* |
| riscv-isa/riscv-privileged-architecture_vol2_ratified_20250508.pdf | The RISC-V Instruction Set Manual: Volume II: Privileged Architecture | 20250508, Ratified (release tag `20250508`, published 2025-05-12) | https://github.com/riscv/riscv-isa-manual/releases/download/20250508/riscv-privileged-20250508.pdf | 1372206 | 221 | d0228bbecc76943a | Ch.2.2 CSR listing, Ch.3.1.7 mtvec, 3.1.9 mip/mie, 3.1.10 Hardware Performance Monitor (mcycle), 3.1.12 mcountinhibit, 3.1.14 mepc, 3.1.15 mcause, 3.1.16 mtval, 3.2.1 mtime/mtimecmp, 3.3.2 trap-return (mret), 3.4 Reset, 3.5 NMI, 3.7 Physical Memory Protection (3.7.1 PMP CSRs) |
| riscv-isa/riscv-external-debug-support_v1.0_20250221.pdf | The RISC-V Debug Specification | 1.0, Ratified, revised 2025-02-21 (release tag `1.0`) | https://github.com/riscv/riscv-debug-spec/releases/download/1.0/riscv-debug-specification.pdf | 2495279 | 119 | ce2787b25233a610 | Ch.3 Debug Module (3.1 DMI, 3.7 abstract commands, 3.8 program buffer, 3.13 version detection, 3.14 DM registers), Ch.4 Sdext (4.1 Debug Mode, 4.5 single step, 4.10 virtual debug registers), Ch.5 Sdtrig triggers (5.7 trigger registers), Ch.6.1 JTAG DTM + dtmcs/dmi, 6.1.7 JTAG connector; 1.2.1.2–1.2.1.4 lists the incompatible changes from 0.13 that Espressif's OpenOCD must work around |
| riscv-isa/riscv-external-debug-support_v0.13.2_20190322.pdf | RISC-V External Debug Support | 0.13.2, 2019-03-22 (repo commit d5029366, built PDF `riscv-debug-release.pdf`) | https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf | 818053 | 94 | f203abb93ee2ad60 | **The version ESP32-P4 actually implements** — TRM states "Debug module (DM) compliant with … RISC-V External Debug Support Version 0.13.2" for the HP DM and "Version 0.13" for the LP DM. Ch.3 Debug Module (3.12 DM registers dmstatus@0x11/dmcontrol@0x10/command@0x17/progbuf0@0x20), Ch.4 core debug registers (dcsr/dpc), Ch.5 Trigger Module, Ch.6 JTAG DTM (dmi@0x11) |
| riscv-isa/riscv-elf-psabi_riscv-abi_draft-20260813.pdf | RISC-V ABIs Specification (psABI: calling convention + ELF) | v1.1, 2026-08-13, "Pre-release" (release tag `draft-20260813-01017c3`) | https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/draft-20260813-01017c343cd6d89ed4d1d568b1c75fac79d2a689/riscv-abi.pdf | 526941 | 118 | ff94b93578a5ee44 | Ch.1.1/1.3 integer + FP register convention, Ch.2.1/2.2 integer and hardware-FP calling convention, Ch.2.7/2.8 named ABIs (ilp32/ilp32f), Ch.5 code models (medlow/medany), Ch.9.1 ELF file header + e_flags, Ch.9.4 relocations (used by the hand-written linker script and LLD), Ch.9.6 sections, Ch.9.7 program header table, Ch.9.11.1 layout of `.riscv.attributes` |
| riscv-isa/riscv-fast-interrupt_clic_draft-v0.10_20250324.pdf | Core-Local Interrupt Controller (CLIC) RISC-V Privileged Architecture Extensions | v0.10, 2025-03-17, **Draft** (release tag `v0.10`, published 2025-03-24 — newest release carrying `clic.pdf`) | https://github.com/riscv/riscv-fast-interrupt/releases/download/v0.10/clic.pdf | 434674 | 69 | ddb80f16aecb98ff | Ch.2 CLIC overview + preemption, Ch.3 `smclic` M-mode extension (3.1 level/priority, 3.2 clicintip, 3.3 clicintie, 3.4 clicintattr, 3.5 clicintctl, 3.8 CLIC CSRs incl. mintthresh/mnxti, 3.9 reset, 3.10 interrupt operation), Ch.5 `smclicshv` selective hardware vectoring, Ch.6 CLIC parameters — the architectural model behind the P4's CLIC/INTPRI |
| riscv-isa/riscv-fast-interrupt_aclic_draft-v0.20_20260731.pdf | Advanced Core-Local Interrupt Controller (ACLIC) RISC-V Privileged Architecture Extensions | v0.20, 2026-07-31, "Stable" but unratified draft (release tag `v0.20`) | https://github.com/riscv/riscv-fast-interrupt/releases/download/v0.20/aclic-v0.20.pdf | 282310 | 38 | 1892f06fd863fe73 | Successor document to CLIC in the same task-group repo; current draft register/CSR model for core-local fast interrupts. Secondary to the v0.10 CLIC PDF for P4 work — the P4 predates it |
| riscv-isa/riscv-assembly-programmers-manual_v0.0.1_20250205.pdf | RISC-V Assembly Programmer's Manual | tag `v0.0.1`, 2025-02-05 (document self-labels "v0.0.0, Development state") | https://github.com/riscv-non-isa/riscv-asm-manual/releases/download/v0.0.1/riscv-asm.pdf | 238665 | 50 | 2edf43ff39c0ca47 | Ch.1 command-line arguments, Ch.2.1/2.2 general + control register naming, plus assembler directives/relocation-modifier syntax used in hand-written startup asm and linker-script-adjacent code |
| riscv-isa/riscv-code-size-reduction_zc_v1.0.4-3_20231026.pdf | Zc* code-size-reduction extension specification | v1.0.4-3, 2023-10-26 (release tag `v1.0.4-3`, riscvarchive) | https://github.com/riscvarchive/riscv-code-size-reduction/releases/download/v1.0.4-3/Zc-1.0.4-3.pdf | 916986 | 60 | 62cea3875763904b | Standalone Zc* doc; §1.1 change history records the `C implies Zca/Zcf/Zcd` and `misa.C` rules that matter when naming the P4's `c` extension in a target triple. Superseded in-tree by Vol I Ch.28 — low priority |
| riscv-isa/riscv-plic_v1.0.0_20230312.pdf | RISC-V Platform-Level Interrupt Controller Specification | 1.0.0, 3/2023, Ratified (release tag `1.0.0`) | https://github.com/riscv/riscv-plic-spec/releases/download/1.0.0/riscv-plic-1.0.0.pdf | 545211 | 18 | 82644c7701601baa | Low relevance — ESP32-P4 uses its own interrupt matrix + CLIC-style controller, not a PLIC; kept only as the contrast point referenced by CLIC §1.3 |
| riscv-isa/riscv-aclint_v1.0-rc4_20220114.pdf | RISC-V Advanced Core Local Interruptor Specification | 1.0-rc4, 2022-01-10, **Draft** (release tag `v1.0-rc4`, riscvarchive; never ratified) | https://github.com/riscvarchive/riscv-aclint/releases/download/v1.0-rc4/riscv-aclint-1.0-rc4.pdf | 133041 | 11 | fb7f1473470fbc2a | Low relevance — Ch.2 MTIMER (mtime/mtimecmp) and Ch.3 MSWI describe the CLINT-style timer the P4 does *not* use (it has systimer/TIMG instead); useful only when comparing against Vol II §3.2.1 |
All 11 files verified: `file` reports "PDF document", `pdfinfo` parses (page counts above), and `pdftotext -f 1 -l 2` shows the expected title and version string on page 1 (e.g. "Version 20250508: This document is in Ratified state.", "Version 1.0, Revised 2025-02-21: Ratified", "RISC-V External Debug Support / Version 0.13.2"). Total directory size 12 MB.
## Not obtained
| wanted | why not | best known pointer |
|---|---|---|
| Debug spec 0.13.2 as a GitHub *release* asset | No release exists for 0.13.2 in `riscv/riscv-debug-spec` (oldest release with an asset is `task_group_vote`, 2018). The obtained file is the official built PDF from riscv.org; it is byte-identical (818053 bytes, sha256 f203abb93ee2ad60) to the repo-hosted `riscv-debug-release.pdf` at the 0.13.2 commit, so provenance is confirmed against github.com/riscv | https://github.com/riscv/riscv-debug-spec/raw/4e0bb0fc2d843473db2356623792c6b7603b94d4/riscv-debug-release.pdf |
| Separate "ELF psABI" PDF distinct from `riscv-abi.pdf` | Does not exist: the repo publishes a single merged artifact ("RISC-V ABIs Specification") whose Ch.9 *is* the ELF psABI. Only `draft-YYYYMMDD-<sha>` releases are published — there is no ratified/non-draft psABI release, so the newest draft was taken | https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases |
| Ratified CLIC / fast-interrupt spec | None exists. The task group has only ever published drafts; releases `v0.9`–`v0.10` carry `clic.pdf`, and `v0.16`–`v0.20` replaced it with `aclic.pdf`. Both newest artifacts of each lineage were taken and are labelled drafts above | https://github.com/riscv/riscv-fast-interrupt/releases (v0.10 = last `clic.pdf`; v0.20 = newest `aclic.pdf`) |
| Newer-than-20250508 ratified ISA manual | Not available. All 700+ newer tags in `riscv/riscv-isa-manual` are automated nightly `riscv-isa-release-<sha>-<date>` builds of the in-development merged `riscv-spec.pdf` (latest 2026-08-24), which are unratified. `20250508` is the newest ratified release and the only recent one shipping split Vol I / Vol II PDFs | https://github.com/riscv/riscv-isa-manual/releases/tag/20250508 |
| Ratified ACLINT 1.0 | Never ratified; repo moved to `riscvarchive` with `v1.0-rc4` (2022) as the final artifact. rc4 fetched and marked low relevance | https://github.com/riscvarchive/riscv-aclint/releases/tag/v1.0-rc4 |
## Belongs elsewhere
- ESP32-P4 Technical Reference Manual (its "RISC-V CPU", "Interrupt Matrix", "CLIC/INTPRI" and "Debug" chapters state DM compliance with debug spec 0.13.2) — should be fetched by `espressif-silicon/`
- Espressif OpenOCD / JTAG debugging manual and GDB usage docs — should be fetched by `espressif-software/`
- Espressif `Xesppie` / PIE custom-instruction documentation and the LP-core (`rv32imac`-class) ISA notes — should be fetched by `espressif-custom-isa/`
|
