path: root/src/net/hosted/sdkconfig_idf.h

/*
 * ESP-IDF v6.0.2's generated Kconfig header, verbatim.
 *
 * Provenance: 00-projects/0x4200.cafe/02-esp32p4-m3-radio/build/config/sdkconfig.h, produced by the
 * IDF build that brought this P4 onto Wi-Fi through the onboard ESP32-C6 over SDIO. Not edited -
 * not one line. Deviations belong in sdkconfig.h, which includes this file and then overrides
 * individual symbols with a reason attached.
 *
 * Do not include this directly. Include "sdkconfig.h", which is what ESP-IDF's own headers ask for.
 */
/*
 * Automatically generated file. DO NOT EDIT.
 * Espressif IoT Development Framework (ESP-IDF) 6.0.2 Configuration Header
 */
#pragma once
#define CONFIG_SOC_ADC_SUPPORTED 1
#define CONFIG_SOC_ANA_CMPR_SUPPORTED 1
#define CONFIG_SOC_DEDICATED_GPIO_SUPPORTED 1
#define CONFIG_SOC_UART_SUPPORTED 1
#define CONFIG_SOC_GDMA_SUPPORTED 1
#define CONFIG_SOC_UHCI_SUPPORTED 1
#define CONFIG_SOC_AHB_GDMA_SUPPORTED 1
#define CONFIG_SOC_AXI_GDMA_SUPPORTED 1
#define CONFIG_SOC_DW_GDMA_SUPPORTED 1
#define CONFIG_SOC_DMA2D_SUPPORTED 1
#define CONFIG_SOC_GPTIMER_SUPPORTED 1
#define CONFIG_SOC_PCNT_SUPPORTED 1
#define CONFIG_SOC_LCDCAM_CAM_SUPPORTED 1
#define CONFIG_SOC_LCDCAM_I80_LCD_SUPPORTED 1
#define CONFIG_SOC_LCDCAM_RGB_LCD_SUPPORTED 1
#define CONFIG_SOC_LCD_I80_SUPPORTED 1
#define CONFIG_SOC_LCD_RGB_SUPPORTED 1
#define CONFIG_SOC_MIPI_CSI_SUPPORTED 1
#define CONFIG_SOC_MIPI_DSI_SUPPORTED 1
#define CONFIG_SOC_MCPWM_SUPPORTED 1
#define CONFIG_SOC_TWAI_SUPPORTED 1
#define CONFIG_SOC_ETM_SUPPORTED 1
#define CONFIG_SOC_PARLIO_SUPPORTED 1
#define CONFIG_SOC_PARLIO_LCD_SUPPORTED 1
#define CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED 1
#define CONFIG_SOC_EMAC_SUPPORTED 1
#define CONFIG_SOC_USB_OTG_SUPPORTED 1
#define CONFIG_SOC_WIRELESS_HOST_SUPPORTED 1
#define CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED 1
#define CONFIG_SOC_TEMP_SENSOR_SUPPORTED 1
#define CONFIG_SOC_SUPPORTS_SECURE_DL_MODE 1
#define CONFIG_SOC_ULP_SUPPORTED 1
#define CONFIG_SOC_LP_CORE_SUPPORTED 1
#define CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define CONFIG_SOC_EFUSE_SUPPORTED 1
#define CONFIG_SOC_RTC_FAST_MEM_SUPPORTED 1
#define CONFIG_SOC_RTC_MEM_SUPPORTED 1
#define CONFIG_SOC_RMT_SUPPORTED 1
#define CONFIG_SOC_I2S_SUPPORTED 1
#define CONFIG_SOC_SDM_SUPPORTED 1
#define CONFIG_SOC_GPSPI_SUPPORTED 1
#define CONFIG_SOC_LEDC_SUPPORTED 1
#define CONFIG_SOC_ISP_SUPPORTED 1
#define CONFIG_SOC_I2C_SUPPORTED 1
#define CONFIG_SOC_SYSTIMER_SUPPORTED 1
#define CONFIG_SOC_AES_SUPPORTED 1
#define CONFIG_SOC_MPI_SUPPORTED 1
#define CONFIG_SOC_SHA_SUPPORTED 1
#define CONFIG_SOC_HMAC_SUPPORTED 1
#define CONFIG_SOC_DIG_SIGN_SUPPORTED 1
#define CONFIG_SOC_ECC_SUPPORTED 1
#define CONFIG_SOC_ECC_EXTENDED_MODES_SUPPORTED 1
#define CONFIG_SOC_ECDSA_SUPPORTED 1
#define CONFIG_SOC_KEY_MANAGER_SUPPORTED 1
#define CONFIG_SOC_HUK_SUPPORTED 1
#define CONFIG_SOC_FLASH_ENC_SUPPORTED 1
#define CONFIG_SOC_SECURE_BOOT_SUPPORTED 1
#define CONFIG_SOC_BOD_SUPPORTED 1
#define CONFIG_SOC_VBAT_SUPPORTED 1
#define CONFIG_SOC_APM_SUPPORTED 1
#define CONFIG_SOC_PMU_SUPPORTED 1
#define CONFIG_SOC_PMU_PVT_SUPPORTED 1
#define CONFIG_SOC_PVT_EN_WITH_SLEEP 1
#define CONFIG_SOC_PVT_RETENTION_BY_REGDMA 1
#define CONFIG_SOC_DCDC_SUPPORTED 1
#define CONFIG_SOC_PAU_SUPPORTED 1
#define CONFIG_SOC_RTC_TIMER_V2_SUPPORTED 1
#define CONFIG_SOC_ULP_LP_UART_SUPPORTED 1
#define CONFIG_SOC_LP_GPIO_MATRIX_SUPPORTED 1
#define CONFIG_SOC_LP_PERIPHERALS_SUPPORTED 1
#define CONFIG_SOC_LP_I2C_SUPPORTED 1
#define CONFIG_SOC_LP_I2S_SUPPORTED 1
#define CONFIG_SOC_LP_SPI_SUPPORTED 1
#define CONFIG_SOC_LP_ADC_SUPPORTED 1
#define CONFIG_SOC_LP_VAD_SUPPORTED 1
#define CONFIG_SOC_LP_MAILBOX_SUPPORTED 1
#define CONFIG_SOC_SPIRAM_SUPPORTED 1
#define CONFIG_SOC_PSRAM_DMA_CAPABLE 1
#define CONFIG_SOC_SDMMC_HOST_SUPPORTED 1
#define CONFIG_SOC_CLK_TREE_SUPPORTED 1
#define CONFIG_SOC_ASSIST_DEBUG_SUPPORTED 1
#define CONFIG_SOC_DEBUG_PROBE_SUPPORTED 1
#define CONFIG_SOC_WDT_SUPPORTED 1
#define CONFIG_SOC_SPI_FLASH_SUPPORTED 1
#define CONFIG_SOC_TOUCH_SENSOR_SUPPORTED 1
#define CONFIG_SOC_RNG_SUPPORTED 1
#define CONFIG_SOC_GP_LDO_SUPPORTED 1
#define CONFIG_SOC_PPA_SUPPORTED 1
#define CONFIG_SOC_LIGHT_SLEEP_SUPPORTED 1
#define CONFIG_SOC_DEEP_SLEEP_SUPPORTED 1
#define CONFIG_SOC_PM_SUPPORTED 1
#define CONFIG_SOC_BITSCRAMBLER_SUPPORTED 1
#define CONFIG_SOC_SIMD_INSTRUCTION_SUPPORTED 1
#define CONFIG_SOC_I3C_MASTER_SUPPORTED 1
#define CONFIG_SOC_XTAL_SUPPORT_40M 1
#define CONFIG_SOC_AES_SUPPORT_DMA 1
#define CONFIG_SOC_AES_SUPPORT_GCM 1
#define CONFIG_SOC_AES_GDMA 1
#define CONFIG_SOC_AES_SUPPORT_AES_128 1
#define CONFIG_SOC_AES_SUPPORT_AES_256 1
#define CONFIG_SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION 1
#define CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED 1
#define CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED 1
#define CONFIG_SOC_ADC_DMA_SUPPORTED 1
#define CONFIG_SOC_ADC_PERIPH_NUM 2
#define CONFIG_SOC_ADC_MAX_CHANNEL_NUM 8
#define CONFIG_SOC_ADC_ATTEN_NUM 4
#define CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM 2
#define CONFIG_SOC_ADC_PATT_LEN_MAX 16
#define CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH 12
#define CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH 12
#define CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM 2
#define CONFIG_SOC_ADC_DIGI_MONITOR_NUM 2
#define CONFIG_SOC_ADC_DIGI_RESULT_BYTES 4
#define CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV 4
#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
#define CONFIG_SOC_ADC_RTC_MIN_BITWIDTH 12
#define CONFIG_SOC_ADC_RTC_MAX_BITWIDTH 12
#define CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED 1
#define CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED 1
#define CONFIG_SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED 1
#define CONFIG_SOC_ADC_SHARED_POWER 1
#define CONFIG_SOC_BROWNOUT_RESET_SUPPORTED 1
#define CONFIG_SOC_SHARED_IDCACHE_SUPPORTED 1
#define CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED 1
#define CONFIG_SOC_CACHE_FREEZE_SUPPORTED 1
#define CONFIG_SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE 1
#define CONFIG_SOC_CPU_CORES_NUM 2
#define CONFIG_SOC_CPU_INTR_NUM 32
#define CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC 1
#define CONFIG_SOC_INT_CLIC_SUPPORTED 1
#define CONFIG_SOC_INT_HW_NESTED_SUPPORTED 1
#define CONFIG_SOC_BRANCH_PREDICTOR_SUPPORTED 1
#define CONFIG_SOC_CPU_COPROC_NUM 3
#define CONFIG_SOC_CPU_HAS_FPU 1
#define CONFIG_SOC_CPU_HAS_FPU_EXT_ILL_BUG 1
#define CONFIG_SOC_CPU_HAS_HWLOOP 1
#define CONFIG_SOC_CPU_HAS_HWLOOP_STATE_BUG 1
#define CONFIG_SOC_CPU_HAS_PIE 1
#define CONFIG_SOC_HP_CPU_HAS_MULTIPLE_CORES 1
#define CONFIG_SOC_CPU_BREAKPOINTS_NUM 3
#define CONFIG_SOC_CPU_WATCHPOINTS_NUM 3
#define CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x100
#define CONFIG_SOC_CPU_HAS_PMA 1
#define CONFIG_SOC_CPU_IDRAM_SPLIT_USING_PMP 1
#define CONFIG_SOC_CPU_PMP_REGION_GRANULARITY 128
#define CONFIG_SOC_CPU_HAS_LOCKUP_RESET 1
#define CONFIG_SOC_CPU_HAS_ZC_EXTENSIONS 1
#define CONFIG_SOC_CPU_ZCMP_WORKAROUND 1
#define CONFIG_SOC_CPU_ZCMP_PUSH_REVERSED 1
#define CONFIG_SOC_CPU_ZCMP_POPRET_ISSUE 1
#define CONFIG_SOC_SIMD_PREFERRED_DATA_ALIGNMENT 16
#define CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN 4096
#define CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH 16
#define CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US 1100
#define CONFIG_SOC_DMA_CAN_ACCESS_FLASH 1
#define CONFIG_SOC_AHB_GDMA_VERSION 2
#define CONFIG_SOC_GDMA_SUPPORT_CRC 1
#define CONFIG_SOC_GDMA_SUPPORT_ETM 1
#define CONFIG_SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_GDMA_EXT_MEM_ENC_ALIGNMENT 16
#define CONFIG_SOC_GPIO_PORT 1
#define CONFIG_SOC_GPIO_PIN_COUNT 55
#define CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define CONFIG_SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
#define CONFIG_SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
#define CONFIG_SOC_GPIO_SUPPORT_ETM 1
#define CONFIG_SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP 1
#define CONFIG_SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE 1
#define CONFIG_SOC_LP_IO_CLOCK_IS_INDEPENDENT 1
#define CONFIG_SOC_GPIO_VALID_GPIO_MASK 0x007FFFFFFFFFFFFF
#define CONFIG_SOC_GPIO_IN_RANGE_MAX 54
#define CONFIG_SOC_GPIO_OUT_RANGE_MAX 54
#define CONFIG_SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK 0
#define CONFIG_SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT 16
#define CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000
#define CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD 1
#define CONFIG_SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP 1
#define CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX 1
#define CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM 2
#define CONFIG_SOC_CLOCKOUT_SUPPORT_CHANNEL_DIVIDER 1
#define CONFIG_SOC_DEBUG_PROBE_NUM_UNIT 1
#define CONFIG_SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH 16
#define CONFIG_SOC_RTCIO_PIN_COUNT 16
#define CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
#define CONFIG_SOC_RTCIO_HOLD_SUPPORTED 1
#define CONFIG_SOC_RTCIO_WAKE_SUPPORTED 1
#define CONFIG_SOC_SDM_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_ETM_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_ANA_CMPR_NUM 2
#define CONFIG_SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE 1
#define CONFIG_SOC_ANA_CMPR_SUPPORT_ETM 1
#define CONFIG_SOC_I2C_NUM 3
#define CONFIG_SOC_HP_I2C_NUM 2
#define CONFIG_SOC_LP_I2C_NUM 1
#define CONFIG_SOC_I2C_SUPPORT_XTAL 1
#define CONFIG_SOC_I2C_SUPPORT_RTC 1
#define CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR 1
#define CONFIG_SOC_I2C_SUPPORT_SLAVE 1
#define CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST 1
#define CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE 1
#define CONFIG_SOC_I2C_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_I2S_HW_VERSION_2 1
#define CONFIG_SOC_I2S_SUPPORTS_ETM 1
#define CONFIG_SOC_I2S_SUPPORTS_APLL 1
#define CONFIG_SOC_I2S_SUPPORTS_PCM 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM_TX 1
#define CONFIG_SOC_I2S_SUPPORTS_PCM2PDM 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM_RX 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM2PCM 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER 1
#define CONFIG_SOC_I2S_SUPPORTS_TX_SYNC_CNT 1
#define CONFIG_SOC_I2S_SUPPORTS_TDM 1
#define CONFIG_SOC_I2S_PDM_MAX_TX_LINES 2
#define CONFIG_SOC_I2S_PDM_MAX_RX_LINES 4
#define CONFIG_SOC_LP_I2S_NUM 1
#define CONFIG_SOC_ISP_BF_SUPPORTED 1
#define CONFIG_SOC_ISP_BLC_SUPPORTED 1
#define CONFIG_SOC_ISP_CCM_SUPPORTED 1
#define CONFIG_SOC_ISP_COLOR_SUPPORTED 1
#define CONFIG_SOC_ISP_CROP_SUPPORTED 1
#define CONFIG_SOC_ISP_DEMOSAIC_SUPPORTED 1
#define CONFIG_SOC_ISP_DVP_SUPPORTED 1
#define CONFIG_SOC_ISP_LSC_SUPPORTED 1
#define CONFIG_SOC_ISP_SHARPEN_SUPPORTED 1
#define CONFIG_SOC_ISP_WBG_SUPPORTED 1
#define CONFIG_SOC_ISP_SHARE_CSI_BRG 1
#define CONFIG_SOC_ISP_AE_BLOCK_X_NUMS 5
#define CONFIG_SOC_ISP_AE_BLOCK_Y_NUMS 5
#define CONFIG_SOC_ISP_AF_WINDOW_NUMS 3
#define CONFIG_SOC_ISP_AWB_WINDOW_X_NUMS 5
#define CONFIG_SOC_ISP_AWB_WINDOW_Y_NUMS 5
#define CONFIG_SOC_ISP_BF_TEMPLATE_X_NUMS 3
#define CONFIG_SOC_ISP_BF_TEMPLATE_Y_NUMS 3
#define CONFIG_SOC_ISP_CCM_DIMENSION 3
#define CONFIG_SOC_ISP_DEMOSAIC_GRAD_RATIO_INT_BITS 2
#define CONFIG_SOC_ISP_DEMOSAIC_GRAD_RATIO_DEC_BITS 4
#define CONFIG_SOC_ISP_DEMOSAIC_GRAD_RATIO_RES_BITS 26
#define CONFIG_SOC_ISP_SHARPEN_TEMPLATE_X_NUMS 3
#define CONFIG_SOC_ISP_SHARPEN_TEMPLATE_Y_NUMS 3
#define CONFIG_SOC_ISP_SHARPEN_H_FREQ_COEF_INT_BITS 3
#define CONFIG_SOC_ISP_SHARPEN_H_FREQ_COEF_DEC_BITS 5
#define CONFIG_SOC_ISP_SHARPEN_H_FREQ_COEF_RES_BITS 24
#define CONFIG_SOC_ISP_SHARPEN_M_FREQ_COEF_INT_BITS 3
#define CONFIG_SOC_ISP_SHARPEN_M_FREQ_COEF_DEC_BITS 5
#define CONFIG_SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS 24
#define CONFIG_SOC_ISP_HIST_BLOCK_X_NUMS 5
#define CONFIG_SOC_ISP_HIST_BLOCK_Y_NUMS 5
#define CONFIG_SOC_ISP_HIST_SEGMENT_NUMS 16
#define CONFIG_SOC_ISP_HIST_INTERVAL_NUMS 15
#define CONFIG_SOC_ISP_LSC_GRAD_RATIO_INT_BITS 2
#define CONFIG_SOC_ISP_LSC_GRAD_RATIO_DEC_BITS 8
#define CONFIG_SOC_ISP_LSC_GRAD_RATIO_RES_BITS 22
#define CONFIG_SOC_LEDC_SUPPORT_PLL_DIV_CLOCK 1
#define CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK 1
#define CONFIG_SOC_LEDC_TIMER_NUM 4
#define CONFIG_SOC_LEDC_CHANNEL_NUM 8
#define CONFIG_SOC_LEDC_TIMER_BIT_WIDTH 20
#define CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED 1
#define CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX 16
#define CONFIG_SOC_LEDC_SUPPORT_FADE_STOP 1
#define CONFIG_SOC_LEDC_FADE_PARAMS_BIT_WIDTH 10
#define CONFIG_SOC_LEDC_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_LEDC_SUPPORT_ETM 1
#define CONFIG_SOC_MMU_PERIPH_NUM 2
#define CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM 2
#define CONFIG_SOC_MMU_DI_VADDR_SHARED 1
#define CONFIG_SOC_MMU_PER_EXT_MEM_TARGET 1
#define CONFIG_SOC_MPU_MIN_REGION_SIZE 0x20000000
#define CONFIG_SOC_MPU_REGIONS_MAX_NUM 8
#define CONFIG_SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
#define CONFIG_SOC_PCNT_SUPPORT_CLEAR_SIGNAL 1
#define CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL 48
#define CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG 1
#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT 1
#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1
#define CONFIG_SOC_RMT_SUPPORT_DMA 1
#define CONFIG_SOC_RMT_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE 1
#define CONFIG_SOC_MCPWM_SUPPORT_ETM 1
#define CONFIG_SOC_MCPWM_SUPPORT_EVENT_COMPARATOR 1
#define CONFIG_SOC_MCPWM_CAPTURE_CLK_FROM_GROUP 1
#define CONFIG_SOC_MCPWM_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_USB_OTG_PERIPH_NUM 2
#define CONFIG_SOC_USB_FSLS_PHY_NUM 1
#define CONFIG_SOC_USB_UTMI_PHY_NUM 1
#define CONFIG_SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO 1
#define CONFIG_SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16
#define CONFIG_SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16
#define CONFIG_SOC_PARLIO_TX_CLK_SUPPORT_GATING 1
#define CONFIG_SOC_PARLIO_RX_CLK_SUPPORT_GATING 1
#define CONFIG_SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION 1
#define CONFIG_SOC_PARLIO_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_PARLIO_SUPPORT_I80_LCD 1
#define CONFIG_SOC_MPI_MEM_BLOCKS_NUM 4
#define CONFIG_SOC_MPI_OPERATIONS_NUM 3
#define CONFIG_SOC_RSA_MAX_BIT_LEN 4096
#define CONFIG_SOC_SDMMC_USE_IOMUX 1
#define CONFIG_SOC_SDMMC_USE_GPIO_MATRIX 1
#define CONFIG_SOC_SDMMC_NUM_SLOTS 2
#define CONFIG_SOC_SDMMC_DATA_WIDTH_MAX 8
#define CONFIG_SOC_SDMMC_DELAY_PHASE_NUM 8
#define CONFIG_SOC_SDMMC_IO_POWER_EXTERNAL 1
#define CONFIG_SOC_SDMMC_PSRAM_DMA_CAPABLE 1
#define CONFIG_SOC_SDMMC_UHS_I_SUPPORTED 1
#define CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE 3968
#define CONFIG_SOC_SHA_SUPPORT_DMA 1
#define CONFIG_SOC_SHA_SUPPORT_RESUME 1
#define CONFIG_SOC_SHA_GDMA 1
#define CONFIG_SOC_SHA_SUPPORT_SHA1 1
#define CONFIG_SOC_SHA_SUPPORT_SHA224 1
#define CONFIG_SOC_SHA_SUPPORT_SHA256 1
#define CONFIG_SOC_SHA_SUPPORT_SHA384 1
#define CONFIG_SOC_SHA_SUPPORT_SHA512 1
#define CONFIG_SOC_SHA_SUPPORT_SHA512_224 1
#define CONFIG_SOC_SHA_SUPPORT_SHA512_256 1
#define CONFIG_SOC_SHA_SUPPORT_SHA512_T 1
#define CONFIG_SOC_ECC_CONSTANT_TIME_POINT_MUL 1
#define CONFIG_SOC_ECC_SUPPORT_CURVE_P384 1
#define CONFIG_SOC_ECDSA_SUPPORT_EXPORT_PUBKEY 1
#define CONFIG_SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE 1
#define CONFIG_SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP 1
#define CONFIG_SOC_ECDSA_USES_MPI 1
#define CONFIG_SOC_ECDSA_SUPPORT_CURVE_P384 1
#define CONFIG_SOC_ECDSA_SUPPORT_CURVE_SPECIFIC_KEY_PURPOSES 1
#define CONFIG_SOC_SPI_PERIPH_NUM 3
#define CONFIG_SOC_SPI_MAX_CS_NUM 6
#define CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define CONFIG_SOC_SPI_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
#define CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define CONFIG_SOC_SPI_SUPPORT_DDRCLK 1
#define CONFIG_SOC_SPI_SUPPORT_CD_SIG 1
#define CONFIG_SOC_SPI_SUPPORT_OCT 1
#define CONFIG_SOC_SPI_SUPPORT_CLK_XTAL 1
#define CONFIG_SOC_SPI_SUPPORT_CLK_RC_FAST 1
#define CONFIG_SOC_MSPI_HAS_INDEPENT_IOMUX 1
#define CONFIG_SOC_MEMSPI_IS_INDEPENDENT 1
#define CONFIG_SOC_SPI_MAX_PRE_DIVIDER 16
#define CONFIG_SOC_LP_SPI_MAXIMUM_BUFFER_SIZE 64
#define CONFIG_SOC_SPIRAM_XIP_SUPPORTED 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_TIMING_TUNING 1
#define CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_DQS 1
#define CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR 1
#define CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
#define CONFIG_SOC_SPI_MEM_FLASH_SUPPORT_HPM 1
#define CONFIG_SOC_MEMSPI_ENCRYPTION_ALIGNMENT 16
#define CONFIG_SOC_SYSTIMER_COUNTER_NUM 2
#define CONFIG_SOC_SYSTIMER_ALARM_NUM 3
#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO 32
#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI 20
#define CONFIG_SOC_SYSTIMER_FIXED_DIVIDER 1
#define CONFIG_SOC_SYSTIMER_SUPPORT_RC_FAST 1
#define CONFIG_SOC_SYSTIMER_INT_LEVEL 1
#define CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1
#define CONFIG_SOC_SYSTIMER_SUPPORT_ETM 1
#define CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO 32
#define CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI 16
#define CONFIG_SOC_TIMER_SUPPORT_ETM 1
#define CONFIG_SOC_TIMER_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_MWDT_SUPPORT_XTAL 1
#define CONFIG_SOC_MWDT_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_TOUCH_SENSOR_VERSION 3
#define CONFIG_SOC_TOUCH_MIN_CHAN_ID 1
#define CONFIG_SOC_TOUCH_MAX_CHAN_ID 14
#define CONFIG_SOC_TOUCH_SUPPORT_SLEEP_WAKEUP 1
#define CONFIG_SOC_TOUCH_SUPPORT_BENCHMARK 1
#define CONFIG_SOC_TOUCH_SUPPORT_WATERPROOF 1
#define CONFIG_SOC_TOUCH_SUPPORT_PROX_SENSING 1
#define CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM 3
#define CONFIG_SOC_TOUCH_SAMPLE_CFG_NUM 3
#define CONFIG_SOC_TWAI_CONTROLLER_NUM 3
#define CONFIG_SOC_TWAI_MASK_FILTER_NUM 1
#define CONFIG_SOC_TWAI_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_EFUSE_DIS_PAD_JTAG 1
#define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1
#define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1
#define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1
#define CONFIG_SOC_EFUSE_DIS_DOWNLOAD_MSPI 1
#define CONFIG_SOC_EFUSE_ECDSA_KEY 1
#define CONFIG_SOC_EFUSE_XTS_AES_KEY_128 1
#define CONFIG_SOC_EFUSE_XTS_AES_KEY_256 1
#define CONFIG_SOC_EFUSE_ECDSA_KEY_P192 1
#define CONFIG_SOC_EFUSE_ECDSA_KEY_P384 1
#define CONFIG_SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT 1
#define CONFIG_SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1
#define CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY 1
#define CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 1
#define CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 1
#define CONFIG_SOC_KEY_MANAGER_HMAC_KEY_DEPLOY 1
#define CONFIG_SOC_KEY_MANAGER_DS_KEY_DEPLOY 1
#define CONFIG_SOC_SECURE_BOOT_V2_RSA 1
#define CONFIG_SOC_SECURE_BOOT_V2_ECC 1
#define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
#define CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX 64
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES 1
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS 1
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128 1
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256 1
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND 1
#define CONFIG_SOC_FLASH_ENCRYPTION_PAGE_CONFIGURABLE 1
#define CONFIG_SOC_PSRAM_ENCRYPTION_SEPARATE_KEY 1
#define CONFIG_SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE 1
#define CONFIG_SOC_RECOVERY_BOOTLOADER_SUPPORTED 1
#define CONFIG_SOC_UART_NUM 6
#define CONFIG_SOC_UART_HP_NUM 5
#define CONFIG_SOC_UART_LP_NUM 1
#define CONFIG_SOC_UART_FIFO_LEN 128
#define CONFIG_SOC_LP_UART_FIFO_LEN 16
#define CONFIG_SOC_UART_BITRATE_MAX 5000000
#define CONFIG_SOC_UART_SUPPORT_RTC_CLK 1
#define CONFIG_SOC_UART_SUPPORT_XTAL_CLK 1
#define CONFIG_SOC_UART_SUPPORT_WAKEUP_INT 1
#define CONFIG_SOC_UART_HAS_LP_UART 1
#define CONFIG_SOC_UART_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN 5
#define CONFIG_SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE 1
#define CONFIG_SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE 1
#define CONFIG_SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE 1
#define CONFIG_SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE 1
#define CONFIG_SOC_LP_I2S_SUPPORT_VAD 1
#define CONFIG_SOC_UHCI_NUM 1
#define CONFIG_SOC_COEX_HW_PTI 1
#define CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE 21
#define CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH 12
#define CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN 1
#define CONFIG_SOC_PM_EXT1_WAKEUP_BY_PMU 1
#define CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_LP_UART_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_CPU_PD 1
#define CONFIG_SOC_PM_SUPPORT_XTAL32K_PD 1
#define CONFIG_SOC_PM_SUPPORT_RC32K_PD 1
#define CONFIG_SOC_PM_SUPPORT_RC_FAST_PD 1
#define CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD 1
#define CONFIG_SOC_PM_SUPPORT_TOP_PD 1
#define CONFIG_SOC_PM_SUPPORT_CNNT_PD 1
#define CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD 1
#define CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY 1
#define CONFIG_SOC_PM_CPU_RETENTION_BY_SW 1
#define CONFIG_SOC_PM_FPU_RETENTION_BY_SW 1
#define CONFIG_SOC_PM_CACHE_RETENTION_BY_PAU 1
#define CONFIG_SOC_PM_PAU_LINK_NUM 4
#define CONFIG_SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR 1
#define CONFIG_SOC_PAU_IN_TOP_DOMAIN 1
#define CONFIG_SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE 1
#define CONFIG_SOC_SLEEP_SYSTIMER_STALL_WORKAROUND 1
#define CONFIG_SOC_SLEEP_TGWDT_STOP_WORKAROUND 1
#define CONFIG_SOC_PM_RETENTION_MODULE_NUM 64
#define CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION 1
#define CONFIG_SOC_CLK_APLL_SUPPORTED 1
#define CONFIG_SOC_CLK_MPLL_SUPPORTED 1
#define CONFIG_SOC_CLK_XTAL32K_SUPPORTED 1
#define CONFIG_SOC_CLK_RC32K_SUPPORTED 1
#define CONFIG_SOC_CLK_LP_FAST_SUPPORT_LP_PLL 1
#define CONFIG_SOC_CLK_LP_FAST_SUPPORT_XTAL 1
#define CONFIG_SOC_PERIPH_CLK_CTRL_SHARED 1
#define CONFIG_SOC_TEMPERATURE_SENSOR_INTR_SUPPORT 1
#define CONFIG_SOC_TSENS_IS_INDEPENDENT_FROM_ADC 1
#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_ETM 1
#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_MEM_SPM_SUPPORTED 1
#define CONFIG_SOC_ASYNCHRONOUS_BUS_ERROR_MODE 1
#define CONFIG_SOC_EMAC_IEEE1588V2_SUPPORTED 1
#define CONFIG_SOC_EMAC_USE_MULTI_IO_MUX 1
#define CONFIG_SOC_EMAC_MII_USE_GPIO_MATRIX 1
#define CONFIG_SOC_EMAC_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_JPEG_CODEC_SUPPORTED 1
#define CONFIG_SOC_JPEG_DECODE_SUPPORTED 1
#define CONFIG_SOC_JPEG_ENCODE_SUPPORTED 1
#define CONFIG_SOC_H264_ENCODER_SUPPORTED 1
#define CONFIG_SOC_LCDCAM_CAM_SUPPORT_RGB_YUV_CONV 1
#define CONFIG_SOC_LCDCAM_LCD_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_I3C_MASTER_PERIPH_NUM 1
#define CONFIG_SOC_I3C_MASTER_ADDRESS_TABLE_NUM 12
#define CONFIG_SOC_I3C_MASTER_COMMAND_TABLE_NUM 12
#define CONFIG_SOC_LP_CORE_SUPPORT_ETM 1
#define CONFIG_SOC_LP_CORE_SUPPORT_LP_ADC 1
#define CONFIG_SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS 1
#define CONFIG_IDF_CMAKE 1
#define CONFIG_IDF_TOOLCHAIN "gcc"
#define CONFIG_IDF_TOOLCHAIN_GCC 1
#define CONFIG_IDF_TARGET_ARCH_RISCV 1
#define CONFIG_IDF_TARGET_ARCH "riscv"
#define CONFIG_IDF_TARGET "esp32p4"
#define CONFIG_IDF_INIT_VERSION "6.0.2"
#define CONFIG_IDF_TARGET_ESP32P4 1
#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0012
#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1
#define CONFIG_APP_BUILD_GENERATE_BINARIES 1
#define CONFIG_APP_BUILD_BOOTLOADER 1
#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
#define CONFIG_BOOTLOADER_COMPILE_TIME_DATE 1
#define CONFIG_BOOTLOADER_PROJECT_VER 1
#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x2000
#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1
#define CONFIG_BOOTLOADER_LOG_VERSION_1 1
#define CONFIG_BOOTLOADER_LOG_VERSION 1
#define CONFIG_BOOTLOADER_LOG_LEVEL_INFO 1
#define CONFIG_BOOTLOADER_LOG_LEVEL 3
#define CONFIG_BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS 1
#define CONFIG_BOOTLOADER_LOG_MODE_TEXT_EN 1
#define CONFIG_BOOTLOADER_LOG_MODE_TEXT 1
#define CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ 90
#define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1
#define CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE 1
#define CONFIG_BOOTLOADER_WDT_ENABLE 1
#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000
#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0
#define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1
#define CONFIG_SECURE_BOOT_V2_ECC_SUPPORTED 1
#define CONFIG_SECURE_BOOT_V2_ECDSA_INSECURE 1
#define CONFIG_SECURE_BOOT_V2_PREFERRED 1
#define CONFIG_SECURE_ROM_DL_MODE_ENABLED 1
#define CONFIG_APP_COMPILE_TIME_DATE 1
#define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 9
#define CONFIG_ESP_ROM_HAS_CRC_LE 1
#define CONFIG_ESP_ROM_HAS_CRC_BE 1
#define CONFIG_ESP_ROM_UART_CLK_IS_XTAL 1
#define CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM 6
#define CONFIG_ESP_ROM_USB_OTG_NUM 5
#define CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING 1
#define CONFIG_ESP_ROM_GET_CLK_FREQ 1
#define CONFIG_ESP_ROM_HAS_RVFPLIB 1
#define CONFIG_ESP_ROM_HAS_HAL_WDT 1
#define CONFIG_ESP_ROM_HAS_HAL_SYSTIMER 1
#define CONFIG_ESP_ROM_SYSTIMER_INIT_PATCH 1
#define CONFIG_ESP_ROM_HAS_LAYOUT_TABLE 1
#define CONFIG_ESP_ROM_WDT_INIT_PATCH 1
#define CONFIG_ESP_ROM_HAS_LP_ROM 1
#define CONFIG_ESP_ROM_WITHOUT_REGI2C 1
#define CONFIG_ESP_ROM_HAS_NEWLIB 1
#define CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT 1
#define CONFIG_ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG 1
#define CONFIG_ESP_ROM_HAS_VERSION 1
#define CONFIG_ESP_ROM_CLIC_INT_TYPE_PATCH 1
#define CONFIG_ESP_ROM_HAS_OUTPUT_PUTC_FUNC 1
#define CONFIG_ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY 1
#define CONFIG_ESP_ROM_ECDSA_VERIFY_PATCH 1
#define CONFIG_ESP_ROM_BOOTLOADER_OFFSET_FLASH 0x2000
#define CONFIG_ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_MAP 1
#define CONFIG_BOOT_ROM_LOG_ALWAYS_ON 1
#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1
#define CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR 1
#define CONFIG_ESPTOOLPY_FLASHMODE "dio"
#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1
#define CONFIG_ESPTOOLPY_FLASHFREQ_VAL 80
#define CONFIG_ESPTOOLPY_FLASHFREQ "80m"
#define CONFIG_ESPTOOLPY_FLASHSIZE_16MB 1
#define CONFIG_ESPTOOLPY_FLASHSIZE "16MB"
#define CONFIG_ESPTOOLPY_BEFORE_RESET 1
#define CONFIG_ESPTOOLPY_BEFORE "default-reset"
#define CONFIG_ESPTOOLPY_AFTER_RESET 1
#define CONFIG_ESPTOOLPY_AFTER "hard-reset"
#define CONFIG_ESPTOOLPY_MONITOR_BAUD 115200
#define CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE 1
#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp_large.csv"
#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
#define CONFIG_PARTITION_TABLE_MD5 1
#define CONFIG_COMPILER_OPTIMIZATION_DEBUG 1
#define CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE 1
#define CONFIG_COMPILER_FLOAT_LIB_FROM_RVFPLIB 1
#define CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL 2
#define CONFIG_COMPILER_HIDE_PATHS_MACROS 1
#define CONFIG_COMPILER_STACK_CHECK_MODE_NONE 1
#define CONFIG_COMPILER_RT_LIB_GCCLIB 1
#define CONFIG_COMPILER_RT_LIB_NAME "gcc"
#define CONFIG_COMPILER_ORPHAN_SECTIONS_ERROR 1
#define CONFIG_COMPILER_CXX_GLIBCXX_CONSTEXPR_NO_CHANGE 1
#define CONFIG_BT_ENABLED 1
#define CONFIG_BT_NIMBLE_ENABLED 1
#define CONFIG_BT_CONTROLLER_DISABLED 1
#define CONFIG_BT_ALARM_MAX_NUM 50
#define CONFIG_BT_SMP_CRYPTO_STACK_TINYCRYPT 1
#define CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL 1
#define CONFIG_BT_NIMBLE_PINNED_TO_CORE 0
#define CONFIG_BT_NIMBLE_PINNED_TO_CORE_0 1
#define CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE 4096
#define CONFIG_BT_NIMBLE_ROLE_PERIPHERAL 1
#define CONFIG_BT_NIMBLE_ROLE_BROADCASTER 1
#define CONFIG_BT_NIMBLE_ROLE_OBSERVER 1
#define CONFIG_BT_NIMBLE_GATT_SERVER 1
#define CONFIG_BT_NIMBLE_SECURITY_ENABLE 1
#define CONFIG_BT_NIMBLE_SM_LEGACY 1
#define CONFIG_BT_NIMBLE_SM_SC 1
#define CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_ENCRYPTION 1
#define CONFIG_BT_NIMBLE_SM_LVL 0
#define CONFIG_BT_NIMBLE_SM_SC_ONLY 0
#define CONFIG_BT_NIMBLE_MAX_BONDS 3
#define CONFIG_BT_NIMBLE_RPA_TIMEOUT 900
#define CONFIG_BT_NIMBLE_WHITELIST_SIZE 12
#define CONFIG_BT_NIMBLE_HS_PVCY 1
#define CONFIG_BT_NIMBLE_MAX_CONNECTIONS 3
#define CONFIG_BT_NIMBLE_MAX_CCCDS 8
#define CONFIG_BT_NIMBLE_HS_STOP_TIMEOUT_MS 2000
#define CONFIG_BT_NIMBLE_USE_ESP_TIMER 1
#define CONFIG_BT_NIMBLE_ATT_PREFERRED_MTU 256
#define CONFIG_BT_NIMBLE_ATT_MAX_PREP_ENTRIES 64
#define CONFIG_BT_NIMBLE_GATT_MAX_PROCS 4
#define CONFIG_BT_NIMBLE_L2CAP_COC_MAX_NUM 0
#define CONFIG_BT_NIMBLE_MSYS_1_BLOCK_COUNT 12
#define CONFIG_BT_NIMBLE_MSYS_1_BLOCK_SIZE 256
#define CONFIG_BT_NIMBLE_MSYS_2_BLOCK_COUNT 24
#define CONFIG_BT_NIMBLE_MSYS_2_BLOCK_SIZE 320
#define CONFIG_BT_NIMBLE_TRANSPORT_ACL_FROM_LL_COUNT 24
#define CONFIG_BT_NIMBLE_TRANSPORT_ACL_SIZE 255
#define CONFIG_BT_NIMBLE_TRANSPORT_EVT_SIZE 70
#define CONFIG_BT_NIMBLE_TRANSPORT_EVT_COUNT 30
#define CONFIG_BT_NIMBLE_TRANSPORT_EVT_DISCARD_COUNT 8
#define CONFIG_BT_NIMBLE_L2CAP_COC_SDU_BUFF_COUNT 1
#define CONFIG_BT_NIMBLE_PROX_SERVICE 1
#define CONFIG_BT_NIMBLE_ANS_SERVICE 1
#define CONFIG_BT_NIMBLE_CTS_SERVICE 1
#define CONFIG_BT_NIMBLE_HTP_SERVICE 1
#define CONFIG_BT_NIMBLE_IPSS_SERVICE 1
#define CONFIG_BT_NIMBLE_TPS_SERVICE 1
#define CONFIG_BT_NIMBLE_IAS_SERVICE 1
#define CONFIG_BT_NIMBLE_LLS_SERVICE 1
#define CONFIG_BT_NIMBLE_SPS_SERVICE 1
#define CONFIG_BT_NIMBLE_HR_SERVICE 1
#define CONFIG_BT_NIMBLE_BAS_SERVICE 1
#define CONFIG_BT_NIMBLE_DIS_SERVICE 1
#define CONFIG_BT_NIMBLE_GAP_SERVICE 1
#define CONFIG_BT_NIMBLE_SVC_GAP_DEVICE_NAME "nimble"
#define CONFIG_BT_NIMBLE_GAP_DEVICE_NAME_MAX_LEN 31
#define CONFIG_BT_NIMBLE_SVC_GAP_APPEARANCE 0x0
#define CONFIG_BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM 0
#define CONFIG_BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM_ENC 0
#define CONFIG_BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM_AUTHEN 0
#define CONFIG_BT_NIMBLE_SVC_GAP_NAME_WRITE_PERM_AUTHOR 0
#define CONFIG_BT_NIMBLE_SVC_GAP_CAR_CHAR_NOT_SUPP 1
#define CONFIG_BT_NIMBLE_SVC_GAP_CENT_ADDR_RESOLUTION -1
#define CONFIG_BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM 0
#define CONFIG_BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ENC 0
#define CONFIG_BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ATHN 0
#define CONFIG_BT_NIMBLE_SVC_GAP_APPEAR_WRITE_PERM_ATHR 0
#define CONFIG_BT_NIMBLE_SVC_GAP_PPCP_MAX_CONN_INTERVAL 0
#define CONFIG_BT_NIMBLE_SVC_GAP_PPCP_MIN_CONN_INTERVAL 0
#define CONFIG_BT_NIMBLE_SVC_GAP_PPCP_SLAVE_LATENCY 0
#define CONFIG_BT_NIMBLE_SVC_GAP_PPCP_SUPERVISION_TMO 0
#define CONFIG_BT_NIMBLE_EATT_CHAN_NUM 0
#define CONFIG_BT_NIMBLE_DTM_MODE_TEST 1
#define CONFIG_BT_NIMBLE_MEM_OPTIMIZATION 1
#define CONFIG_BT_NIMBLE_STATIC_TO_DYNAMIC 1
#define CONFIG_BT_NIMBLE_SM_SIGN_CNT 1
#define CONFIG_BT_NIMBLE_CPFD_CAFD 1
#define CONFIG_BT_NIMBLE_RECONFIG_MTU 1
#define CONFIG_UART_HW_FLOWCTRL_DISABLE 1
#define CONFIG_BT_NIMBLE_HCI_UART_FLOW_CTRL 0
#define CONFIG_BT_NIMBLE_HCI_UART_RTS_PIN 19
#define CONFIG_BT_NIMBLE_HCI_UART_CTS_PIN 23
#define CONFIG_BT_NIMBLE_LOG_LEVEL_INFO 1
#define CONFIG_BT_NIMBLE_LOG_LEVEL 1
#define CONFIG_BT_NIMBLE_PRINT_ERR_NAME 1
#define CONFIG_BT_NIMBLE_CHK_HOST_STATUS 1
#define CONFIG_BT_NIMBLE_UTIL_API 1
#define CONFIG_BT_NIMBLE_EXTRA_ADV_FIELDS 1
#define CONFIG_EFUSE_MAX_BLK_LEN 256
#define CONFIG_ESP_TLS_USING_MBEDTLS 1
#define CONFIG_ESP_TLS_USE_DS_PERIPHERAL 1
#define CONFIG_ESP_TLS_DYN_BUF_STRATEGY_SUPPORTED 1
#define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1
#define CONFIG_ANA_CMPR_ISR_HANDLER_IN_IRAM 1
#define CONFIG_ANA_CMPR_OBJ_CACHE_SAFE 1
#define CONFIG_GDMA_CTRL_FUNC_IN_IRAM 1
#define CONFIG_GDMA_ISR_HANDLER_IN_IRAM 1
#define CONFIG_GDMA_OBJ_DRAM_SAFE 1
#define CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM 1
#define CONFIG_GPTIMER_OBJ_CACHE_SAFE 1
#define CONFIG_I2C_MASTER_ISR_HANDLER_IN_IRAM 1
#define CONFIG_MCPWM_ISR_HANDLER_IN_IRAM 1
#define CONFIG_MCPWM_OBJ_CACHE_SAFE 1
#define CONFIG_PARLIO_TX_ISR_HANDLER_IN_IRAM 1
#define CONFIG_PARLIO_RX_ISR_HANDLER_IN_IRAM 1
#define CONFIG_PARLIO_OBJ_CACHE_SAFE 1
#define CONFIG_RMT_ENCODER_FUNC_IN_IRAM 1
#define CONFIG_RMT_TX_ISR_HANDLER_IN_IRAM 1
#define CONFIG_RMT_RX_ISR_HANDLER_IN_IRAM 1
#define CONFIG_RMT_OBJ_CACHE_SAFE 1
#define CONFIG_SPI_MASTER_ISR_IN_IRAM 1
#define CONFIG_SPI_SLAVE_ISR_IN_IRAM 1
#define CONFIG_USJ_ENABLE_USB_SERIAL_JTAG 1
#define CONFIG_ETH_ENABLED 1
#define CONFIG_ETH_USE_ESP32_EMAC 1
#define CONFIG_ETH_DMA_BUFFER_SIZE 512
#define CONFIG_ETH_DMA_RX_BUFFER_NUM 20
#define CONFIG_ETH_DMA_TX_BUFFER_NUM 10
#define CONFIG_ETH_USE_SPI_ETHERNET 1
#define CONFIG_ESP_EVENT_POST_FROM_ISR 1
#define CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR 1
#define CONFIG_ESP_GDBSTUB_ENABLED 1
#define CONFIG_ESP_GDBSTUB_SUPPORT_TASKS 1
#define CONFIG_ESP_GDBSTUB_MAX_TASKS 32
#define CONFIG_ESPHID_TASK_SIZE_BT 2048
#define CONFIG_ESPHID_TASK_SIZE_BLE 4096
#define CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS 1
#define CONFIG_ESP_HTTP_CLIENT_EVENT_POST_TIMEOUT 2000
#define CONFIG_HTTPD_MAX_REQ_HDR_LEN 1024
#define CONFIG_HTTPD_MAX_URI_LEN 512
#define CONFIG_HTTPD_ERR_RESP_NO_DELAY 1
#define CONFIG_HTTPD_PURGE_BUF_LEN 32
#define CONFIG_HTTPD_SERVER_EVENT_POST_TIMEOUT 2000
#define CONFIG_ESP_HTTPS_OTA_EVENT_POST_TIMEOUT 2000
#define CONFIG_ESP_HTTPS_SERVER_EVENT_POST_TIMEOUT 2000
#define CONFIG_ESP_HW_SUPPORT_FUNC_IN_IRAM 1
#define CONFIG_ESP32P4_SELECTS_REV_LESS_V3 1
#define CONFIG_ESP32P4_REV_MIN_100 1
#define CONFIG_ESP32P4_REV_MIN_FULL 100
#define CONFIG_ESP_REV_MIN_FULL 100
#define CONFIG_ESP32P4_REV_MAX_FULL 199
#define CONFIG_ESP_REV_MAX_FULL 199
#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0
#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 199
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
#define CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_ONE 1
#define CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES 1
#define CONFIG_ESP32P4_UNIVERSAL_MAC_ADDRESSES_ONE 1
#define CONFIG_ESP32P4_UNIVERSAL_MAC_ADDRESSES 1
#define CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND 1
#define CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND 1
#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1
#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 0
#define CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS 1
#define CONFIG_RTC_CLK_SRC_INT_RC 1
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
#define CONFIG_RTC_FAST_CLK_SRC_RC_FAST 1
#define CONFIG_RTC_CLK_FUNC_IN_IRAM 1
#define CONFIG_RTC_TIME_FUNC_IN_IRAM 1
#define CONFIG_ESP_PERIPH_CTRL_FUNC_IN_IRAM 1
#define CONFIG_ESP_REGI2C_CTRL_FUNC_IN_IRAM 1
#define CONFIG_XTAL_FREQ_40 1
#define CONFIG_XTAL_FREQ 40
#define CONFIG_ESP_SLEEP_DCM_VSET_VAL_IN_SLEEP 14
#define CONFIG_ESP_LDO_RESERVE_SPI_NOR_FLASH 1
#define CONFIG_ESP_LDO_CHAN_SPI_NOR_FLASH_DOMAIN 1
#define CONFIG_ESP_LDO_VOLTAGE_SPI_NOR_FLASH_3300_MV 1
#define CONFIG_ESP_LDO_VOLTAGE_SPI_NOR_FLASH_DOMAIN 3300
#define CONFIG_ESP_LDO_RESERVE_PSRAM 1
#define CONFIG_ESP_LDO_CHAN_PSRAM_DOMAIN 2
#define CONFIG_ESP_LDO_VOLTAGE_PSRAM_1800_MV 1
#define CONFIG_ESP_LDO_VOLTAGE_PSRAM_DOMAIN 1800
#define CONFIG_ESP_BROWNOUT_DET 1
#define CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 1
#define CONFIG_ESP_BROWNOUT_DET_LVL 7
#define CONFIG_ESP_BROWNOUT_USE_INTR 1
#define CONFIG_ESP_SPI_BUS_LOCK_ISR_FUNCS_IN_IRAM 1
#define CONFIG_ESP_ENABLE_PVT 1
#define CONFIG_ESP_INTR_IN_IRAM 1
#define CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE 0x0
#define CONFIG_LCD_DSI_ISR_HANDLER_IN_IRAM 1
#define CONFIG_LCD_DSI_OBJ_FORCE_INTERNAL 1
#define CONFIG_LIBC_PICOLIBC 1
#define CONFIG_LIBC_PICOLIBC_NEWLIB_COMPATIBILITY 1
#define CONFIG_LIBC_MISC_IN_IRAM 1
#define CONFIG_LIBC_LOCKS_PLACE_IN_IRAM 1
#define CONFIG_LIBC_STDOUT_LINE_ENDING_CRLF 1
#define CONFIG_LIBC_STDIN_LINE_ENDING_CR 1
#define CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT 1
#define CONFIG_LIBC_OPTIMIZED_MISALIGNED_ACCESS 1
#define CONFIG_LIBC_ASSERT_BUFFER_SIZE 200
#define CONFIG_ESP_NETIF_LOST_IP_TIMER_ENABLE 1
#define CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL 120
#define CONFIG_ESP_NETIF_TCPIP_LWIP 1
#define CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API 1
#define CONFIG_ESP_NETIF_REPORT_DATA_TRAFFIC 1
#define CONFIG_ESP_NETIF_RECEIVE_REPORT_ERRORS 1
#define CONFIG_PM_SLEEP_FUNC_IN_IRAM 1
#define CONFIG_PM_SLP_IRAM_OPT 1
#define CONFIG_PM_SLP_DEFAULT_PARAMS_OPT 1
#define CONFIG_SPIRAM 1
#define CONFIG_SPIRAM_MODE_HEX 1
#define CONFIG_SPIRAM_SPEED_200M 1
#define CONFIG_SPIRAM_SPEED 200
#define CONFIG_SPIRAM_BOOT_HW_INIT 1
#define CONFIG_SPIRAM_BOOT_INIT 1
#define CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION 1
#define CONFIG_SPIRAM_USE_MALLOC 1
#define CONFIG_SPIRAM_MEMTEST 1
#define CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL 16384
#define CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL 32768
#define CONFIG_ESP_ROM_PRINT_IN_IRAM 1
#define CONFIG_ESP_CONSOLE_UART_DEFAULT 1
#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1
#define CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED 1
#define CONFIG_ESP_CONSOLE_UART 1
#define CONFIG_ESP_CONSOLE_UART_NUM 0
#define CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM 0
#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_360 1
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 360
#define CONFIG_CACHE_L2_CACHE_128KB 1
#define CONFIG_CACHE_L2_CACHE_SIZE 0x20000
#define CONFIG_CACHE_L2_CACHE_LINE_64B 1
#define CONFIG_CACHE_L2_CACHE_LINE_SIZE 64
#define CONFIG_CACHE_L1_CACHE_LINE_SIZE 64
#define CONFIG_ESP_SYSTEM_IN_IRAM 1
#define CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT 1
#define CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS 0
#define CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK 1
#define CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 1
#define CONFIG_ESP_SYSTEM_NO_BACKTRACE 1
#define CONFIG_ESP_SYSTEM_MEMPROT 1
#define CONFIG_ESP_SYSTEM_MEMPROT_PMP 1
#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32
#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2304
#define CONFIG_ESP_MAIN_TASK_STACK_SIZE 6144
#define CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0 1
#define CONFIG_ESP_MAIN_TASK_AFFINITY 0x0
#define CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE 2048
#define CONFIG_ESP_INT_WDT 1
#define CONFIG_ESP_INT_WDT_TIMEOUT_MS 300
#define CONFIG_ESP_INT_WDT_CHECK_CPU1 1
#define CONFIG_ESP_TASK_WDT_EN 1
#define CONFIG_ESP_TASK_WDT_INIT 1
#define CONFIG_ESP_TASK_WDT_TIMEOUT_S 5
#define CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 1
#define CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 1
#define CONFIG_ESP_DEBUG_OCDAWARE 1
#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
#define CONFIG_ESP_SYSTEM_HW_STACK_GUARD 1
#define CONFIG_ESP_SYSTEM_HW_PC_RECORD 1
#define CONFIG_ESP_IPC_ENABLE 1
#define CONFIG_ESP_IPC_TASK_STACK_SIZE 1024
#define CONFIG_ESP_IPC_USES_CALLERS_PRIORITY 1
#define CONFIG_ESP_IPC_ISR_ENABLE 1
#define CONFIG_ESP_TIMER_IN_IRAM 1
#define CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER 1
#define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1
#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584
#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1
#define CONFIG_ESP_TIMER_TASK_AFFINITY 0x0
#define CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0 1
#define CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0 1
#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1
#define CONFIG_ESP_TRACE_LIB_NONE 1
#define CONFIG_ESP_TRACE_LIB_NAME "none"
#define CONFIG_ESP_TRACE_TRANSPORT_NONE 1
#define CONFIG_ESP_TRACE_TRANSPORT_NAME "none"
#define CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM 10
#define CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM 32
#define CONFIG_ESP_WIFI_TX_BUFFER_TYPE 1
#define CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM 32
#define CONFIG_ESP_WIFI_DYNAMIC_RX_MGMT_BUF 0
#define CONFIG_ESP_WIFI_RX_MGMT_BUF_NUM_DEF 5
#define CONFIG_ESP_WIFI_AMPDU_TX_ENABLED 1
#define CONFIG_ESP_WIFI_TX_BA_WIN 6
#define CONFIG_ESP_WIFI_AMPDU_RX_ENABLED 1
#define CONFIG_ESP_WIFI_RX_BA_WIN 6
#define CONFIG_ESP_WIFI_NVS_ENABLED 1
#define CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN 752
#define CONFIG_ESP_WIFI_MGMT_SBUF_NUM 32
#define CONFIG_ESP_WIFI_IRAM_OPT 1
#define CONFIG_ESP_WIFI_EXTRA_IRAM_OPT 1
#define CONFIG_ESP_WIFI_RX_IRAM_OPT 1
#define CONFIG_ESP_WIFI_ENABLE_WPA3_SAE 1
#define CONFIG_ESP_WIFI_ENABLE_SAE_H2E 1
#define CONFIG_ESP_WIFI_ENABLE_SAE_PK 1
#define CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT 1
#define CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA 1
#define CONFIG_ESP_WIFI_WPA3_COMPATIBLE_SUPPORT 1
#define CONFIG_ESP_WIFI_SLP_IRAM_OPT 1
#define CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME 50
#define CONFIG_ESP_WIFI_BSS_MAX_IDLE_SUPPORT 1
#define CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME 10
#define CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME 15
#define CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE 1
#define CONFIG_ESP_WIFI_GMAC_SUPPORT 1
#define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1
#define CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM 7
#define CONFIG_ESP_WIFI_MBEDTLS_CRYPTO 1
#define CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT 1
#define CONFIG_ESP_WIFI_TX_HETB_QUEUE_NUM 3
#define CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT 1
#define CONFIG_ESP_COREDUMP_ENABLE_TO_NONE 1
#define CONFIG_FATFS_VOLUME_COUNT 2
#define CONFIG_FATFS_LFN_HEAP 1
#define CONFIG_FATFS_SECTOR_4096 1
#define CONFIG_FATFS_CODEPAGE_437 1
#define CONFIG_FATFS_CODEPAGE 437
#define CONFIG_FATFS_MAX_LFN 255
#define CONFIG_FATFS_API_ENCODING_ANSI_OEM 1
#define CONFIG_FATFS_FS_LOCK 0
#define CONFIG_FATFS_TIMEOUT_MS 10000
#define CONFIG_FATFS_PER_FILE_CACHE 1
#define CONFIG_FATFS_ALLOC_PREFER_EXTRAM 1
#define CONFIG_FATFS_USE_STRFUNC_NONE 1
#define CONFIG_FATFS_VFS_FSTAT_BLKSIZE 0
#define CONFIG_FATFS_LINK_LOCK 1
#define CONFIG_FATFS_USE_DYN_BUFFERS 1
#define CONFIG_FATFS_DONT_TRUST_FREE_CLUSTER_CNT 0
#define CONFIG_FATFS_DONT_TRUST_LAST_ALLOC 0
#define CONFIG_FREERTOS_HZ 1000
#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY 1
#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1
#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1536
#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16
#define CONFIG_FREERTOS_USE_TIMERS 1
#define CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME "Tmr Svc"
#define CONFIG_FREERTOS_TIMER_TASK_NO_AFFINITY 1
#define CONFIG_FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY 0x7FFFFFFF
#define CONFIG_FREERTOS_TIMER_TASK_PRIORITY 1
#define CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH 2048
#define CONFIG_FREERTOS_TIMER_QUEUE_LENGTH 10
#define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0
#define CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES 1
#define CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER 1
#define CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS 1
#define CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER 1
#define CONFIG_FREERTOS_ISR_STACKSIZE 1536
#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1
#define CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER 1
#define CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1 1
#define CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER 1
#define CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM 1
#define CONFIG_FREERTOS_PORT 1
#define CONFIG_FREERTOS_NO_AFFINITY 0x7FFFFFFF
#define CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION 1
#define CONFIG_FREERTOS_DEBUG_OCDAWARE 1
#define CONFIG_FREERTOS_NUMBER_OF_CORES 2
#define CONFIG_HAL_ASSERTION_EQUALS_SYSTEM 1
#define CONFIG_HAL_DEFAULT_ASSERTION_LEVEL 2
#define CONFIG_HAL_SYSTIMER_USE_ROM_IMPL 1
#define CONFIG_HAL_WDT_USE_ROM_IMPL 1
#define CONFIG_HAL_GPIO_USE_ROM_IMPL 1
#define CONFIG_HEAP_POISONING_DISABLED 1
#define CONFIG_HEAP_TRACING_OFF 1
#define CONFIG_LOG_VERSION_1 1
#define CONFIG_LOG_VERSION 1
#define CONFIG_LOG_DEFAULT_LEVEL_INFO 1
#define CONFIG_LOG_DEFAULT_LEVEL 3
#define CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT 1
#define CONFIG_LOG_MAXIMUM_LEVEL 3
#define CONFIG_LOG_DYNAMIC_LEVEL_CONTROL 1
#define CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST 1
#define CONFIG_LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP 1
#define CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_SIZE 31
#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1
#define CONFIG_LOG_MODE_TEXT_EN 1
#define CONFIG_LOG_MODE_TEXT 1
#define CONFIG_LOG_IN_IRAM 1
#define CONFIG_LWIP_ENABLE 1
#define CONFIG_LWIP_LOCAL_HOSTNAME "espressif"
#define CONFIG_LWIP_TCPIP_TASK_PRIO 18
#define CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES 1
#define CONFIG_LWIP_TIMERS_ONDEMAND 1
#define CONFIG_LWIP_ND6 1
#define CONFIG_LWIP_MAX_SOCKETS 10
#define CONFIG_LWIP_SO_REUSE 1
#define CONFIG_LWIP_SO_REUSE_RXTOALL 1
#define CONFIG_LWIP_IP_DEFAULT_TTL 64
#define CONFIG_LWIP_IP4_FRAG 1
#define CONFIG_LWIP_IP6_FRAG 1
#define CONFIG_LWIP_IP_REASS_MAX_PBUFS 10
#define CONFIG_LWIP_IPV6_DUP_DETECT_ATTEMPTS 1
#define CONFIG_LWIP_ESP_GRATUITOUS_ARP 1
#define CONFIG_LWIP_GARP_TMR_INTERVAL 60
#define CONFIG_LWIP_ESP_MLDV6_REPORT 1
#define CONFIG_LWIP_MLDV6_TMR_INTERVAL 40
#define CONFIG_LWIP_TCPIP_RECVMBOX_SIZE 32
#define CONFIG_LWIP_DHCP_DOES_ARP_CHECK 1
#define CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID 1
#define CONFIG_LWIP_DHCP_OPTIONS_LEN 69
#define CONFIG_LWIP_NUM_NETIF_CLIENT_DATA 0
#define CONFIG_LWIP_DHCP_COARSE_TIMER_SECS 1
#define CONFIG_LWIP_DHCPS 1
#define CONFIG_LWIP_DHCPS_REPORT_CLIENT_HOSTNAME 1
#define CONFIG_LWIP_DHCPS_LEASE_UNIT 60
#define CONFIG_LWIP_DHCPS_MAX_STATION_NUM 8
#define CONFIG_LWIP_DHCPS_MAX_HOSTNAME_LEN 64
#define CONFIG_LWIP_DHCPS_STATIC_ENTRIES 1
#define CONFIG_LWIP_IPV4 1
#define CONFIG_LWIP_IPV6 1
#define CONFIG_LWIP_IPV6_NUM_ADDRESSES 3
#define CONFIG_LWIP_NETIF_LOOPBACK 1
#define CONFIG_LWIP_LOOPBACK_MAX_PBUFS 8
#define CONFIG_LWIP_MAX_ACTIVE_TCP 16
#define CONFIG_LWIP_MAX_LISTENING_TCP 16
#define CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION 1
#define CONFIG_LWIP_TCP_MAXRTX 12
#define CONFIG_LWIP_TCP_SYNMAXRTX 12
#define CONFIG_LWIP_TCP_MSS 1440
#define CONFIG_LWIP_TCP_TMR_INTERVAL 250
#define CONFIG_LWIP_TCP_MSL 60000
#define CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT 20000
#define CONFIG_LWIP_TCP_SND_BUF_DEFAULT 5760
#define CONFIG_LWIP_TCP_WND_DEFAULT 5760
#define CONFIG_LWIP_TCP_RECVMBOX_SIZE 6
#define CONFIG_LWIP_TCP_ACCEPTMBOX_SIZE 6
#define CONFIG_LWIP_TCP_QUEUE_OOSEQ 1
#define CONFIG_LWIP_TCP_OOSEQ_TIMEOUT 6
#define CONFIG_LWIP_TCP_OOSEQ_MAX_PBUFS 4
#define CONFIG_LWIP_TCP_OVERSIZE_MSS 1
#define CONFIG_LWIP_TCP_RTO_TIME 1500
#define CONFIG_LWIP_MAX_UDP_PCBS 16
#define CONFIG_LWIP_UDP_RECVMBOX_SIZE 6
#define CONFIG_LWIP_CHECKSUM_CHECK_ICMP 1
#define CONFIG_LWIP_TCPIP_TASK_STACK_SIZE 3072
#define CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY 1
#define CONFIG_LWIP_TCPIP_TASK_AFFINITY 0x7FFFFFFF
#define CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE 3
#define CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS 5
#define CONFIG_LWIP_IPV6_ND6_NUM_PREFIXES 5
#define CONFIG_LWIP_IPV6_ND6_NUM_ROUTERS 3
#define CONFIG_LWIP_IPV6_ND6_NUM_DESTINATIONS 10
#define CONFIG_LWIP_ICMP 1
#define CONFIG_LWIP_MAX_RAW_PCBS 16
#define CONFIG_LWIP_SNTP_MAX_SERVERS 1
#define CONFIG_LWIP_SNTP_UPDATE_DELAY 3600000
#define CONFIG_LWIP_SNTP_STARTUP_DELAY 1
#define CONFIG_LWIP_SNTP_MAXIMUM_STARTUP_DELAY 5000
#define CONFIG_LWIP_DNS_MAX_HOST_IP 1
#define CONFIG_LWIP_DNS_MAX_SERVERS 3
#define CONFIG_LWIP_BRIDGEIF_MAX_PORTS 7
#define CONFIG_LWIP_ESP_LWIP_ASSERT 1
#define CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT 1
#define CONFIG_LWIP_HOOK_IP6_ROUTE_NONE 1
#define CONFIG_LWIP_HOOK_ND6_GET_GW_NONE 1
#define CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE 1
#define CONFIG_LWIP_HOOK_DHCP_EXTRA_OPTION_NONE 1
#define CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE 1
#define CONFIG_LWIP_HOOK_DNS_EXT_RESOLVE_NONE 1
#define CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT 1
#define CONFIG_MBEDTLS_VER_4_X_SUPPORT 1
#define CONFIG_MBEDTLS_COMPILER_OPTIMIZATION_SIZE 1
#define CONFIG_MBEDTLS_FS_IO 1
#define CONFIG_MBEDTLS_THREADING_C 1
#define CONFIG_MBEDTLS_THREADING_PTHREAD 1
#define CONFIG_MBEDTLS_ERROR_STRINGS 1
#define CONFIG_MBEDTLS_VERSION_C 1
#define CONFIG_MBEDTLS_HAVE_TIME 1
#define CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC 1
#define CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN 1
#define CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN 16384
#define CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN 4096
#define CONFIG_MBEDTLS_SELF_TEST 1
#define CONFIG_MBEDTLS_X509_USE_C 1
#define CONFIG_MBEDTLS_PEM_PARSE_C 1
#define CONFIG_MBEDTLS_PEM_WRITE_C 1
#define CONFIG_MBEDTLS_PK_C 1
#define CONFIG_MBEDTLS_PK_PARSE_C 1
#define CONFIG_MBEDTLS_PK_WRITE_C 1
#define CONFIG_MBEDTLS_X509_CRL_PARSE_C 1
#define CONFIG_MBEDTLS_X509_CRT_PARSE_C 1
#define CONFIG_MBEDTLS_X509_CSR_PARSE_C 1
#define CONFIG_MBEDTLS_X509_RSASSA_PSS_SUPPORT 1
#define CONFIG_MBEDTLS_ASN1_PARSE_C 1
#define CONFIG_MBEDTLS_ASN1_WRITE_C 1
#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE 1
#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL 1
#define CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS 200
#define CONFIG_MBEDTLS_TLS_ENABLED 1
#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_2 1
#define CONFIG_MBEDTLS_TLS_SERVER 1
#define CONFIG_MBEDTLS_TLS_CLIENT 1
#define CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT 1
#define CONFIG_MBEDTLS_SSL_CACHE_C 1
#define CONFIG_MBEDTLS_SSL_ALL_ALERT_MESSAGES 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA 1
#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA 1
#define CONFIG_MBEDTLS_SSL_SERVER_NAME_INDICATION 1
#define CONFIG_MBEDTLS_SSL_ALPN 1
#define CONFIG_MBEDTLS_SSL_MAX_FRAGMENT_LENGTH 1
#define CONFIG_MBEDTLS_SSL_RENEGOTIATION 1
#define CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS 1
#define CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS 1
#define CONFIG_MBEDTLS_AES_C 1
#define CONFIG_MBEDTLS_CCM_C 1
#define CONFIG_MBEDTLS_CIPHER_MODE_CBC 1
#define CONFIG_MBEDTLS_CIPHER_MODE_CFB 1
#define CONFIG_MBEDTLS_CIPHER_MODE_CTR 1
#define CONFIG_MBEDTLS_CIPHER_MODE_OFB 1
#define CONFIG_MBEDTLS_CIPHER_MODE_XTS 1
#define CONFIG_MBEDTLS_GCM_C 1
#define CONFIG_MBEDTLS_AES_ROM_TABLES 1
#define CONFIG_MBEDTLS_CMAC_C 1
#define CONFIG_MBEDTLS_RSA_C 1
#define CONFIG_MBEDTLS_ECP_C 1
#define CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED 1
#define CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED 1
#define CONFIG_MBEDTLS_ECP_NIST_OPTIM 1
#define CONFIG_MBEDTLS_ECDH_C 1
#define CONFIG_MBEDTLS_ECDSA_C 1
#define CONFIG_MBEDTLS_PK_PARSE_EC_EXTENDED 1
#define CONFIG_MBEDTLS_PK_PARSE_EC_COMPRESSED 1
#define CONFIG_MBEDTLS_ECDSA_DETERMINISTIC 1
#define CONFIG_MBEDTLS_MD_C 1
#define CONFIG_MBEDTLS_MD5_C 1
#define CONFIG_MBEDTLS_SHA1_C 1
#define CONFIG_MBEDTLS_SHA256_C 1
#define CONFIG_MBEDTLS_SHA384_C 1
#define CONFIG_MBEDTLS_SHA512_C 1
#define CONFIG_MBEDTLS_ROM_MD5 1
#define CONFIG_MBEDTLS_HARDWARE_ECDSA_VERIFY 1
#define CONFIG_MBEDTLS_HARDWARE_ECC 1
#define CONFIG_MBEDTLS_ECC_OTHER_CURVES_SOFT_FALLBACK 1
#define CONFIG_MBEDTLS_HARDWARE_SHA 1
#define CONFIG_MBEDTLS_HARDWARE_MPI 1
#define CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI 1
#define CONFIG_MBEDTLS_MPI_USE_INTERRUPT 1
#define CONFIG_MBEDTLS_MPI_INTERRUPT_LEVEL 0
#define CONFIG_MBEDTLS_HARDWARE_AES 1
#define CONFIG_MBEDTLS_HARDWARE_GCM 1
#define CONFIG_MBEDTLS_GCM_SUPPORT_NON_AES_CIPHER 1
#define CONFIG_MBEDTLS_AES_USE_INTERRUPT 1
#define CONFIG_MBEDTLS_AES_INTERRUPT_LEVEL 0
#define CONFIG_MBEDTLS_AES_HW_SMALL_DATA_LEN_OPTIM 1
#define CONFIG_MBEDTLS_HARDWARE_RSA_DS_PERIPHERAL 1
#define CONFIG_MBEDTLS_CTR_DRBG_C 1
#define CONFIG_MBEDTLS_HMAC_DRBG_C 1
#define CONFIG_MBEDTLS_BASE64_C 1
#define CONFIG_MBEDTLS_PKCS5_C 1
#define CONFIG_MBEDTLS_PKCS7_C 1
#define CONFIG_MBEDTLS_PKCS1_V15 1
#define CONFIG_MBEDTLS_PKCS1_V21 1
#define CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2 1
#define CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_PATCH_VERSION 1
#define CONFIG_PTHREAD_TASK_PRIO_DEFAULT 5
#define CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT 3072
#define CONFIG_PTHREAD_STACK_MIN 768
#define CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY 1
#define CONFIG_PTHREAD_TASK_CORE_DEFAULT -1
#define CONFIG_PTHREAD_TASK_NAME_DEFAULT "pthread"
#define CONFIG_SD_ENABLE_SDIO_SUPPORT 1
#define CONFIG_MMU_PAGE_SIZE_64KB 1
#define CONFIG_MMU_PAGE_MODE "64KB"
#define CONFIG_MMU_PAGE_SIZE 0x10000
#define CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC 1
#define CONFIG_SPI_FLASH_BROWNOUT_RESET 1
#define CONFIG_SPI_FLASH_HPM_AUTO 1
#define CONFIG_SPI_FLASH_HPM_ON 1
#define CONFIG_SPI_FLASH_HPM_DC_AUTO 1
#define CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US 50
#define CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM 1
#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1
#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1
#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20
#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1
#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192
#define CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED 1
#define CONFIG_SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED 1
#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP 1
#define CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE 1
#define CONFIG_SPIFFS_MAX_PARTITIONS 3
#define CONFIG_SPIFFS_CACHE 1
#define CONFIG_SPIFFS_CACHE_WR 1
#define CONFIG_SPIFFS_PAGE_CHECK 1
#define CONFIG_SPIFFS_GC_MAX_RUNS 10
#define CONFIG_SPIFFS_PAGE_SIZE 256
#define CONFIG_SPIFFS_OBJ_NAME_LEN 32
#define CONFIG_SPIFFS_USE_MAGIC 1
#define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1
#define CONFIG_SPIFFS_META_LENGTH 4
#define CONFIG_SPIFFS_USE_MTIME 1
#define CONFIG_WS_TRANSPORT 1
#define CONFIG_WS_BUFFER_SIZE 1024
#define CONFIG_UNITY_ENABLE_FLOAT 1
#define CONFIG_UNITY_ENABLE_DOUBLE 1
#define CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER 1
#define CONFIG_VFS_SUPPORT_IO 1
#define CONFIG_VFS_SUPPORT_DIR 1
#define CONFIG_VFS_SUPPORT_SELECT 1
#define CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT 1
#define CONFIG_VFS_MAX_COUNT 8
#define CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS 1
#define CONFIG_VFS_INITIALIZE_DEV_NULL 1
#define CONFIG_WL_SECTOR_SIZE_4096 1
#define CONFIG_WL_SECTOR_SIZE 4096
#define CONFIG_EPPP_LINK_DEVICE_UART 1
#define CONFIG_EPPP_LINK_CONN_MAX_RETRY 6
#define CONFIG_ESP_HOSTED_ENABLED 1
#define CONFIG_ESP_HOSTED_CP_TARGET_ESP32C6 1
#define CONFIG_ESP_HOSTED_PRIV_ENABLE_WIFI_OPTIONS 1
#define CONFIG_ESP_HOSTED_IDF_SLAVE_TARGET "esp32c6"
#define CONFIG_ESP_HOSTED_P4_DEV_BOARD_NONE 1
#define CONFIG_ESP_HOSTED_PRIV_SDIO_OPTION 1
#define CONFIG_ESP_HOSTED_PRIV_SPI_HD_OPTION 1
#define CONFIG_ESP_HOSTED_SDIO_HOST_INTERFACE 1
#define CONFIG_ESP_HOSTED_SDIO_RESET_ACTIVE_HIGH 1
#define CONFIG_ESP_HOSTED_SDIO_OPTIMIZATION_RX_STREAMING_MODE 1
#define CONFIG_ESP_HOSTED_SDIO_SLOT_1 1
#define CONFIG_ESP_HOSTED_SDIO_SLOT 1
#define CONFIG_ESP_HOSTED_SDIO_4_BIT_BUS 1
#define CONFIG_ESP_HOSTED_SDIO_BUS_WIDTH 4
#define CONFIG_ESP_HOSTED_SDIO_CLOCK_FREQ_KHZ 40000
#define CONFIG_ESP_HOSTED_SDIO_CMD_GPIO_RANGE_MIN 0
#define CONFIG_ESP_HOSTED_SDIO_CMD_GPIO_RANGE_MAX 100
#define CONFIG_ESP_HOSTED_SDIO_CLK_GPIO_RANGE_MIN 0
#define CONFIG_ESP_HOSTED_SDIO_CLK_GPIO_RANGE_MAX 100
#define CONFIG_ESP_HOSTED_SDIO_D0_GPIO_RANGE_MIN 0
#define CONFIG_ESP_HOSTED_SDIO_D0_GPIO_RANGE_MAX 100
#define CONFIG_ESP_HOSTED_SDIO_D1_GPIO_RANGE_MIN 0
#define CONFIG_ESP_HOSTED_SDIO_D1_GPIO_RANGE_MAX 100
#define CONFIG_ESP_HOSTED_SDIO_D2_GPIO_RANGE_MIN 0
#define CONFIG_ESP_HOSTED_SDIO_D2_GPIO_RANGE_MAX 100
#define CONFIG_ESP_HOSTED_SDIO_D3_GPIO_RANGE_MIN 0
#define CONFIG_ESP_HOSTED_SDIO_D3_GPIO_RANGE_MAX 100
#define CONFIG_ESP_HOSTED_SDIO_RESET_SLAVE_GPIO_MIN 0
#define CONFIG_ESP_HOSTED_SDIO_RESET_SLAVE_GPIO_MAX 100
#define CONFIG_ESP_HOSTED_PRIV_SDIO_PIN_CMD_SLOT_1 19
#define CONFIG_ESP_HOSTED_PRIV_SDIO_PIN_CLK_SLOT_1 18
#define CONFIG_ESP_HOSTED_PRIV_SDIO_PIN_D0_SLOT_1 14
#define CONFIG_ESP_HOSTED_PRIV_SDIO_PIN_D1_4BIT_BUS_SLOT_1 15
#define CONFIG_ESP_HOSTED_PRIV_SDIO_PIN_D2_4BIT_BUS_SLOT_1 16
#define CONFIG_ESP_HOSTED_PRIV_SDIO_PIN_D3_4BIT_BUS_SLOT_1 17
#define CONFIG_ESP_HOSTED_SDIO_GPIO_RESET_SLAVE 54
#define CONFIG_ESP_HOSTED_SDIO_PIN_CMD 19
#define CONFIG_ESP_HOSTED_SDIO_PIN_CLK 18
#define CONFIG_ESP_HOSTED_SDIO_PIN_D0 14
#define CONFIG_ESP_HOSTED_SDIO_PRIV_PIN_D1_4BIT_BUS 15
#define CONFIG_ESP_HOSTED_SDIO_PIN_D2 16
#define CONFIG_ESP_HOSTED_SDIO_PIN_D3 17
#define CONFIG_ESP_HOSTED_SDIO_PIN_D1 15
#define CONFIG_ESP_HOSTED_SDIO_TX_Q_SIZE 20
#define CONFIG_ESP_HOSTED_SDIO_RX_Q_SIZE 20
#define CONFIG_ESP_HOSTED_SDIO_RESET_DELAY_MS 1500
#define CONFIG_ESP_HOSTED_SLAVE_RESET_ON_EVERY_HOST_BOOTUP 1
#define CONFIG_ESP_HOSTED_GPIO_SLAVE_RESET_SLAVE 54
#define CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE 1
#define CONFIG_ESP_HOSTED_NIMBLE_HCI_VHCI 1
#define CONFIG_ESP_HOSTED_RPC_TASK_STACK 4096
#define CONFIG_ESP_HOSTED_DFLT_TASK_STACK 3072
#define CONFIG_ESP_HOSTED_TRANSPORT_RESTART_ON_FAILURE 1
#define CONFIG_ESP_HOSTED_MEM_MONITOR 1
#define CONFIG_ESP_HOSTED_ENABLE_ITWT 1
#define CONFIG_ESP_HOSTED_USE_MEMPOOL 1
#define CONFIG_ESP_HOSTED_MAX_SIMULTANEOUS_SYNC_RPC_REQUESTS 5
#define CONFIG_ESP_HOSTED_MAX_SIMULTANEOUS_ASYNC_RPC_REQUESTS 5
#define CONFIG_ESP_HOSTED_CLI_ENABLED 1
#define CONFIG_ESP_HOSTED_HOST_TO_ESP_WIFI_DATA_THROTTLE 1
#define CONFIG_ESP_HOSTED_PRIV_WIFI_TX_SDIO_HIGH_THRESHOLD 80
#define CONFIG_ESP_HOSTED_TO_WIFI_DATA_THROTTLE_HIGH_THRESHOLD 80
#define CONFIG_ESP_HOSTED_TO_WIFI_DATA_THROTTLE_LOW_THRESHOLD 60
#define CONFIG_ESP_HOSTED_ENABLE_PEER_DATA_TRANSFER 1
#define CONFIG_ESP_HOSTED_MAX_CUSTOM_MSG_HANDLERS 3
#define CONFIG_ESP_WIFI_REMOTE_ENABLED 1
#define CONFIG_ESP_WIFI_REMOTE_IDF_SPECIFIC_ADDED 1
#define CONFIG_SLAVE_IDF_TARGET_ESP32C6 1
#define CONFIG_SLAVE_SOC_WIFI_SUPPORTED 1
#define CONFIG_SLAVE_SOC_WIFI_WAPI_SUPPORT 1
#define CONFIG_SLAVE_SOC_WIFI_CSI_SUPPORT 1
#define CONFIG_SLAVE_SOC_WIFI_MESH_SUPPORT 1
#define CONFIG_SLAVE_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH 12
#define CONFIG_SLAVE_SOC_WIFI_HW_TSF 1
#define CONFIG_SLAVE_SOC_WIFI_FTM_SUPPORT 1
#define CONFIG_SLAVE_FREERTOS_UNICORE 1
#define CONFIG_SLAVE_SOC_WIFI_GCMP_SUPPORT 1
#define CONFIG_SLAVE_SOC_WIFI_TXOP_SUPPORT 1
#define CONFIG_SLAVE_IDF_TARGET_ARCH_RISCV 1
#define CONFIG_SLAVE_SOC_WIFI_HE_SUPPORT 1
#define CONFIG_SLAVE_SOC_WIFI_MAC_VERSION_NUM 2
#define CONFIG_WIFI_RMT_STATIC_RX_BUFFER_NUM 10
#define CONFIG_WIFI_RMT_DYNAMIC_RX_BUFFER_NUM 32
#define CONFIG_WIFI_RMT_DYNAMIC_TX_BUFFER 1
#define CONFIG_WIFI_RMT_TX_BUFFER_TYPE 1
#define CONFIG_WIFI_RMT_DYNAMIC_TX_BUFFER_NUM 32
#define CONFIG_WIFI_RMT_STATIC_RX_MGMT_BUFFER 1
#define CONFIG_WIFI_RMT_DYNAMIC_RX_MGMT_BUF 0
#define CONFIG_WIFI_RMT_RX_MGMT_BUF_NUM_DEF 5
#define CONFIG_WIFI_RMT_AMPDU_TX_ENABLED 1
#define CONFIG_WIFI_RMT_TX_BA_WIN 6
#define CONFIG_WIFI_RMT_AMPDU_RX_ENABLED 1
#define CONFIG_WIFI_RMT_RX_BA_WIN 6
#define CONFIG_WIFI_RMT_NVS_ENABLED 1
#define CONFIG_WIFI_RMT_SOFTAP_BEACON_MAX_LEN 752
#define CONFIG_WIFI_RMT_MGMT_SBUF_NUM 32
#define CONFIG_WIFI_RMT_IRAM_OPT 1
#define CONFIG_WIFI_RMT_EXTRA_IRAM_OPT 1
#define CONFIG_WIFI_RMT_RX_IRAM_OPT 1
#define CONFIG_WIFI_RMT_ENABLE_WPA3_SAE 1
#define CONFIG_WIFI_RMT_ENABLE_SAE_H2E 1
#define CONFIG_WIFI_RMT_ENABLE_SAE_PK 1
#define CONFIG_WIFI_RMT_SOFTAP_SAE_SUPPORT 1
#define CONFIG_WIFI_RMT_ENABLE_WPA3_OWE_STA 1
#define CONFIG_WIFI_RMT_WPA3_COMPATIBLE_SUPPORT 1
#define CONFIG_WIFI_RMT_SLP_IRAM_OPT 1
#define CONFIG_WIFI_RMT_SLP_DEFAULT_MIN_ACTIVE_TIME 50
#define CONFIG_WIFI_RMT_BSS_MAX_IDLE_SUPPORT 1
#define CONFIG_WIFI_RMT_SLP_DEFAULT_MAX_ACTIVE_TIME 10
#define CONFIG_WIFI_RMT_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME 15
#define CONFIG_WIFI_RMT_STA_DISCONNECTED_PM_ENABLE 1
#define CONFIG_WIFI_RMT_GMAC_SUPPORT 1
#define CONFIG_WIFI_RMT_SOFTAP_SUPPORT 1
#define CONFIG_WIFI_RMT_ESPNOW_MAX_ENCRYPT_NUM 7
#define CONFIG_WIFI_RMT_MBEDTLS_CRYPTO 1
#define CONFIG_WIFI_RMT_MBEDTLS_TLS_CLIENT 1
#define CONFIG_WIFI_RMT_TX_HETB_QUEUE_NUM 3
#define CONFIG_WIFI_RMT_ENTERPRISE_SUPPORT 1
#define CONFIG_ESP_WIFI_REMOTE_LIBRARY_HOSTED 1
#define CONFIG_ESP_WIFI_REMOTE_EAP_ENABLED 1

/* List of deprecated options */
#define CONFIG_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET
#define CONFIG_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL
#define CONFIG_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
#define CONFIG_BT_NIMBLE_ACL_BUF_COUNT CONFIG_BT_NIMBLE_TRANSPORT_ACL_FROM_LL_COUNT
#define CONFIG_BT_NIMBLE_ACL_BUF_SIZE CONFIG_BT_NIMBLE_TRANSPORT_ACL_SIZE
#define CONFIG_BT_NIMBLE_HCI_EVT_BUF_SIZE CONFIG_BT_NIMBLE_TRANSPORT_EVT_SIZE
#define CONFIG_BT_NIMBLE_HCI_EVT_HI_BUF_COUNT CONFIG_BT_NIMBLE_TRANSPORT_EVT_COUNT
#define CONFIG_BT_NIMBLE_HCI_EVT_LO_BUF_COUNT CONFIG_BT_NIMBLE_TRANSPORT_EVT_DISCARD_COUNT
#define CONFIG_BT_NIMBLE_MSYS1_BLOCK_COUNT CONFIG_BT_NIMBLE_MSYS_1_BLOCK_COUNT
#define CONFIG_BT_NIMBLE_SM_SC_LVL CONFIG_BT_NIMBLE_SM_LVL
#define CONFIG_BT_NIMBLE_TASK_STACK_SIZE CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE
#define CONFIG_COMPILER_OPTIMIZATION_DEFAULT CONFIG_COMPILER_OPTIMIZATION_DEBUG
#define CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEBUG
#define CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART
#define CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE
#define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT
#define CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM
#define CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY
#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE CONFIG_ESP_COREDUMP_ENABLE_TO_NONE
#define CONFIG_ESP32_PTHREAD_STACK_MIN CONFIG_PTHREAD_STACK_MIN
#define CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT CONFIG_PTHREAD_TASK_CORE_DEFAULT
#define CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT CONFIG_PTHREAD_TASK_NAME_DEFAULT
#define CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT CONFIG_PTHREAD_TASK_PRIO_DEFAULT
#define CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT
#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED CONFIG_ESP_WIFI_AMPDU_RX_ENABLED
#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED CONFIG_ESP_WIFI_AMPDU_TX_ENABLED
#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM
#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM
#define CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA
#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE CONFIG_ESP_WIFI_ENABLE_WPA3_SAE
#define CONFIG_ESP32_WIFI_IRAM_OPT CONFIG_ESP_WIFI_IRAM_OPT
#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM CONFIG_ESP_WIFI_MGMT_SBUF_NUM
#define CONFIG_ESP32_WIFI_NVS_ENABLED CONFIG_ESP_WIFI_NVS_ENABLED
#define CONFIG_ESP32_WIFI_RX_BA_WIN CONFIG_ESP_WIFI_RX_BA_WIN
#define CONFIG_ESP32_WIFI_RX_IRAM_OPT CONFIG_ESP_WIFI_RX_IRAM_OPT
#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN
#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM
#define CONFIG_ESP32_WIFI_TX_BA_WIN CONFIG_ESP_WIFI_TX_BA_WIN
#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE CONFIG_ESP_WIFI_TX_BUFFER_TYPE
#define CONFIG_ESP_DFLT_TASK_STACK CONFIG_ESP_HOSTED_DFLT_TASK_STACK
#define CONFIG_ESP_ENABLE_BT_NIMBLE CONFIG_ESP_HOSTED_ENABLE_BT_NIMBLE
#define CONFIG_ESP_GPIO_SLAVE_RESET_SLAVE CONFIG_ESP_HOSTED_GPIO_SLAVE_RESET_SLAVE
#define CONFIG_ESP_GRATUITOUS_ARP CONFIG_LWIP_ESP_GRATUITOUS_ARP
#define CONFIG_ESP_MAX_SIMULTANEOUS_ASYNC_RPC_REQUESTS CONFIG_ESP_HOSTED_MAX_SIMULTANEOUS_ASYNC_RPC_REQUESTS
#define CONFIG_ESP_MAX_SIMULTANEOUS_SYNC_RPC_REQUESTS CONFIG_ESP_HOSTED_MAX_SIMULTANEOUS_SYNC_RPC_REQUESTS
#define CONFIG_ESP_NIMBLE_HCI_VHCI CONFIG_ESP_HOSTED_NIMBLE_HCI_VHCI
#define CONFIG_ESP_RPC_TASK_STACK CONFIG_ESP_HOSTED_RPC_TASK_STACK
#define CONFIG_ESP_SDIO_4_BIT_BUS CONFIG_ESP_HOSTED_SDIO_4_BIT_BUS
#define CONFIG_ESP_SDIO_BUS_WIDTH CONFIG_ESP_HOSTED_SDIO_BUS_WIDTH
#define CONFIG_ESP_SDIO_CLOCK_FREQ_KHZ CONFIG_ESP_HOSTED_SDIO_CLOCK_FREQ_KHZ
#define CONFIG_ESP_SDIO_GPIO_RESET_SLAVE CONFIG_ESP_HOSTED_SDIO_GPIO_RESET_SLAVE
#define CONFIG_ESP_SDIO_HOST_INTERFACE CONFIG_ESP_HOSTED_SDIO_HOST_INTERFACE
#define CONFIG_ESP_SDIO_OPTIMIZATION_RX_STREAMING_MODE CONFIG_ESP_HOSTED_SDIO_OPTIMIZATION_RX_STREAMING_MODE
#define CONFIG_ESP_SDIO_PIN_CLK CONFIG_ESP_HOSTED_SDIO_PIN_CLK
#define CONFIG_ESP_SDIO_PIN_CMD CONFIG_ESP_HOSTED_SDIO_PIN_CMD
#define CONFIG_ESP_SDIO_PIN_D0 CONFIG_ESP_HOSTED_SDIO_PIN_D0
#define CONFIG_ESP_SDIO_PIN_D1 CONFIG_ESP_HOSTED_SDIO_PIN_D1
#define CONFIG_ESP_SDIO_PIN_D2 CONFIG_ESP_HOSTED_SDIO_PIN_D2
#define CONFIG_ESP_SDIO_PIN_D3 CONFIG_ESP_HOSTED_SDIO_PIN_D3
#define CONFIG_ESP_SDIO_RX_Q_SIZE CONFIG_ESP_HOSTED_SDIO_RX_Q_SIZE
#define CONFIG_ESP_SDIO_TX_Q_SIZE CONFIG_ESP_HOSTED_SDIO_TX_Q_SIZE
#define CONFIG_ESP_SYSTEM_BROWNOUT_INTR CONFIG_ESP_BROWNOUT_USE_INTR
#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE CONFIG_ESP_SYSTEM_MEMPROT
#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_VIA_TEE CONFIG_ESP_SYSTEM_MEMPROT
#define CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT CONFIG_ESP_SYSTEM_MEMPROT
#define CONFIG_ESP_TASK_WDT CONFIG_ESP_TASK_WDT_INIT
#define CONFIG_ESP_USE_MEMPOOL CONFIG_ESP_HOSTED_USE_MEMPOOL
#define CONFIG_FLASHMODE_DIO CONFIG_ESPTOOLPY_FLASHMODE_DIO
#define CONFIG_GARP_TMR_INTERVAL CONFIG_LWIP_GARP_TMR_INTERVAL
#define CONFIG_GDBSTUB_MAX_TASKS CONFIG_ESP_GDBSTUB_MAX_TASKS
#define CONFIG_GDBSTUB_SUPPORT_TASKS CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
#define CONFIG_HOST_TO_ESP_WIFI_DATA_THROTTLE CONFIG_ESP_HOSTED_HOST_TO_ESP_WIFI_DATA_THROTTLE
#define CONFIG_IDF_SLAVE_TARGET CONFIG_ESP_HOSTED_IDF_SLAVE_TARGET
#define CONFIG_INT_WDT CONFIG_ESP_INT_WDT
#define CONFIG_INT_WDT_CHECK_CPU1 CONFIG_ESP_INT_WDT_CHECK_CPU1
#define CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS
#define CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE
#define CONFIG_LOG_BOOTLOADER_LEVEL CONFIG_BOOTLOADER_LOG_LEVEL
#define CONFIG_LOG_BOOTLOADER_LEVEL_INFO CONFIG_BOOTLOADER_LOG_LEVEL_INFO
#define CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE
#define CONFIG_MONITOR_BAUD CONFIG_ESPTOOLPY_MONITOR_BAUD
#define CONFIG_NEWLIB_STDIN_LINE_ENDING_CR CONFIG_LIBC_STDIN_LINE_ENDING_CR
#define CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF CONFIG_LIBC_STDOUT_LINE_ENDING_CRLF
#define CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT
#define CONFIG_NIMBLE_ATT_PREFERRED_MTU CONFIG_BT_NIMBLE_ATT_PREFERRED_MTU
#define CONFIG_NIMBLE_ENABLED CONFIG_BT_NIMBLE_ENABLED
#define CONFIG_NIMBLE_GAP_DEVICE_NAME_MAX_LEN CONFIG_BT_NIMBLE_GAP_DEVICE_NAME_MAX_LEN
#define CONFIG_NIMBLE_L2CAP_COC_MAX_NUM CONFIG_BT_NIMBLE_L2CAP_COC_MAX_NUM
#define CONFIG_NIMBLE_MAX_BONDS CONFIG_BT_NIMBLE_MAX_BONDS
#define CONFIG_NIMBLE_MAX_CCCDS CONFIG_BT_NIMBLE_MAX_CCCDS
#define CONFIG_NIMBLE_MAX_CONNECTIONS CONFIG_BT_NIMBLE_MAX_CONNECTIONS
#define CONFIG_NIMBLE_MEM_ALLOC_MODE_INTERNAL CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL
#define CONFIG_NIMBLE_PINNED_TO_CORE CONFIG_BT_NIMBLE_PINNED_TO_CORE
#define CONFIG_NIMBLE_PINNED_TO_CORE_0 CONFIG_BT_NIMBLE_PINNED_TO_CORE_0
#define CONFIG_NIMBLE_ROLE_BROADCASTER CONFIG_BT_NIMBLE_ROLE_BROADCASTER
#define CONFIG_NIMBLE_ROLE_OBSERVER CONFIG_BT_NIMBLE_ROLE_OBSERVER
#define CONFIG_NIMBLE_ROLE_PERIPHERAL CONFIG_BT_NIMBLE_ROLE_PERIPHERAL
#define CONFIG_NIMBLE_RPA_TIMEOUT CONFIG_BT_NIMBLE_RPA_TIMEOUT
#define CONFIG_NIMBLE_SM_LEGACY CONFIG_BT_NIMBLE_SM_LEGACY
#define CONFIG_NIMBLE_SM_SC CONFIG_BT_NIMBLE_SM_SC
#define CONFIG_NIMBLE_SVC_GAP_APPEARANCE CONFIG_BT_NIMBLE_SVC_GAP_APPEARANCE
#define CONFIG_NIMBLE_SVC_GAP_DEVICE_NAME CONFIG_BT_NIMBLE_SVC_GAP_DEVICE_NAME
#define CONFIG_NIMBLE_TASK_STACK_SIZE CONFIG_BT_NIMBLE_HOST_TASK_STACK_SIZE
#define CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE
#define CONFIG_OPTIMIZATION_ASSERTION_LEVEL CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL
#define CONFIG_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEBUG
#define CONFIG_PERIPH_CTRL_FUNC_IN_IRAM CONFIG_ESP_PERIPH_CTRL_FUNC_IN_IRAM
#define CONFIG_POST_EVENTS_FROM_IRAM_ISR CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR
#define CONFIG_POST_EVENTS_FROM_ISR CONFIG_ESP_EVENT_POST_FROM_ISR
#define CONFIG_PRIV_WIFI_TX_SDIO_HIGH_THRESHOLD CONFIG_ESP_HOSTED_PRIV_WIFI_TX_SDIO_HIGH_THRESHOLD
#define CONFIG_SDIO_RESET_ACTIVE_HIGH CONFIG_ESP_HOSTED_SDIO_RESET_ACTIVE_HIGH
#define CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS
#define CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS
#define CONFIG_STACK_CHECK_NONE CONFIG_COMPILER_STACK_CHECK_MODE_NONE
#define CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT
#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE
#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE
#define CONFIG_TASK_WDT CONFIG_ESP_TASK_WDT_INIT
#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
#define CONFIG_TASK_WDT_TIMEOUT_S CONFIG_ESP_TASK_WDT_TIMEOUT_S
#define CONFIG_TCPIP_RECVMBOX_SIZE CONFIG_LWIP_TCPIP_RECVMBOX_SIZE
#define CONFIG_TCPIP_TASK_AFFINITY CONFIG_LWIP_TCPIP_TASK_AFFINITY
#define CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY
#define CONFIG_TCPIP_TASK_STACK_SIZE CONFIG_LWIP_TCPIP_TASK_STACK_SIZE
#define CONFIG_TCP_MAXRTX CONFIG_LWIP_TCP_MAXRTX
#define CONFIG_TCP_MSL CONFIG_LWIP_TCP_MSL
#define CONFIG_TCP_MSS CONFIG_LWIP_TCP_MSS
#define CONFIG_TCP_OVERSIZE_MSS CONFIG_LWIP_TCP_OVERSIZE_MSS
#define CONFIG_TCP_QUEUE_OOSEQ CONFIG_LWIP_TCP_QUEUE_OOSEQ
#define CONFIG_TCP_RECVMBOX_SIZE CONFIG_LWIP_TCP_RECVMBOX_SIZE
#define CONFIG_TCP_SND_BUF_DEFAULT CONFIG_LWIP_TCP_SND_BUF_DEFAULT
#define CONFIG_TCP_SYNMAXRTX CONFIG_LWIP_TCP_SYNMAXRTX
#define CONFIG_TCP_WND_DEFAULT CONFIG_LWIP_TCP_WND_DEFAULT
#define CONFIG_TIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH
#define CONFIG_TIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY
#define CONFIG_TIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH
#define CONFIG_TIMER_TASK_STACK_SIZE CONFIG_ESP_TIMER_TASK_STACK_SIZE
#define CONFIG_TO_WIFI_DATA_THROTTLE_HIGH_THRESHOLD CONFIG_ESP_HOSTED_TO_WIFI_DATA_THROTTLE_HIGH_THRESHOLD
#define CONFIG_TO_WIFI_DATA_THROTTLE_LOW_THRESHOLD CONFIG_ESP_HOSTED_TO_WIFI_DATA_THROTTLE_LOW_THRESHOLD
#define CONFIG_UDP_RECVMBOX_SIZE CONFIG_LWIP_UDP_RECVMBOX_SIZE
#define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO
#define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT